I'd have to dig out the documentation, but I think Tilera addressed some of the Transputer's link limitations by having five (and six in the TilePro64) separate

I'd have to dig out the documentation, but I think Tilera addressed some of the Transputer's link limitations by having five (and six in the TilePro64) separate communications meshes between the cores. There's one mesh each for: memory access, packet transfers, user data network, cache misses, and IPC. The Pro added a cache coherency mesh too. Sadly, Tilera was bought by EZChip, who were bought by Mellanox, who were bought by NVIDIA, and the Tilera processors don't seem to be available or being updated.