3 ms·
Massively parallel was just an marketing buzzword that was used for a lot of different things. One thing to look for is wether all the compute elements run from
by dfox 5y ago
Massively parallel was just an marketing buzzword that was used for a lot of different things. One thing to look for is wether all the compute elements run from same clock or not.
CM1/2 is SIMD machine that is mostly nothing more than FPGA turned inside out and in fact just an accelerator that cannot do anything useful standalone (control flow is mostly done in software on the frontend machine). In this regard it is somewhat similar to today's GPUs.
SP/2 is more or less equivalent of the "Beowulf clusters" of the turn of certury and Slashdot fame, that is bunch of computers with full OS instances connected together with some reasonably fast network. But done few years before on somewhat specialized IBM hardware (And well, Myrinet of the early large Linux based clusters was kind of funky specialized hardware, with these 18pair Cat5 cables...).
CM5 is weird as it is cluster of more or less off the shelf SPARC nodes with several independent communications networks with one of the networks being capable of doing bunch of "collective communications" (reduce, broadcast...) operations in hardware. As with CM1/2 it does not run any kind of OS and is mostly managed by some set of frontend computers than do the job setup and network configuration for each new job.
And then transputer is not an concept, there was real hardware and solar system is full of things that are directly descended from that hardware. The issue with transputers as an HPC platform (even for the early 90's) is that the nodes are too small, slow and have too slow interconnect to be meaningfully usable as general purpose HPC platform because you end up using significant fraction of the potential performance for housekeeping tasks (notice that above mentioned CM1/2/5 has some out of band method for the frontend to manage the nodes and even directly access their local memory, on transputers this had to be done through the main communication network and supported by software running on the nodes themselves, which makes even booting the thing an interesting excercise in parallel programming).
- __d 5y agoI'd have to dig out the documentation, but I think Tilera addressed some of the Transputer's link limitations by having five (and six in the TilePro64) separate communications meshes between the cores. There's one mesh each for: memory access, packet transfers, user data network, cache misses, and IPC. The Pro added a cache coherency mesh too. Sadly, Tilera was bought by EZChip, who were bought by Mellanox, who were bought by NVIDIA, and the Tilera processors don't seem to be available or being updated.