They disabled it because it's not compatible with their efficiency-core design for big.LITTLE - right now, you either have to put AVX-512 on both, or neither.

They disabled it because it's not compatible with their efficiency-core design for big.LITTLE - right now, you either have to put AVX-512 on both, or neither. An efficiency core with AVX-512 is basically a Xeon Phi core (and that approach actually probably would be good at the compute-heavy workloads efficiency cores are optimized for), so that's not an absurdity, but they didn't do that. So at that point the answer is "neither", and they turned it off on their big cores. But apparently they left the unit there in the silicon eating up a fairly large amount of space (I think it's around 10-20% of the core). The real question is why nobody thought of this before... did they have some hardware/software solution to handle the instruction set differences that didn't work out? The fact that it was shoddily disabled before launch, and left in programmers' guides and other documents, speaks that maybe there was something like that and somehow it didn't end up happening. (You could trap instruction errors and mark the thread as big-core-only, the Linux kernel did that at one point for AVX instructions in general (to save registers/bandwidth/etc they wouldn't save the AVX registers unless a thread actually used AVX). But there's more problems that still have to be solved first - how does software know how many AVX-aware cores are available? How does software know which core their CPUID instruction will be executed on? etc etc.) If they had a heterogenous-ISA mechanism or something that will be introduced later, why isn't it on the roadmaps for next-gen/etc. And they didn't have those mechanisms, then why is it still on the core on an extremely high-volume consumer architecture? You could say maybe it's a testbed for Sapphire Rapids, but every company has dedicated test silicon for that, and 10-20% of every single consumer chip sold is a huge waste of money. Sure, they'd have to design a core without it, but Intel absolutely has the money to do that - just like Skylake vs Skylake-X. The unit is designed to be modular so it's not hard, and they'd make it back extremely quickly. Maybe they just needed some dead silicon to spread out the thermal load a bit? Obviously dead silicon has to be dead, so it doesn't matter if you print AVX-512 or the names of the design team, it's not supposed to be powered up either way. Anyway that's my take - the "why take it back off" part is straightforward, the answer is big.LITTLE. The real interesting question is "so why is it still on the silicon".