people kinda oversell the complexity of the situation. like ooh big scary venn diagram right? https://twitter.com/InstLatX64/status/1114141314441011200/photo/

people kinda oversell the complexity of the situation. like ooh big scary venn diagram right? https://twitter.com/InstLatX64/status/1114141314441011200/photo/1 https://twitter.com/InstLatX64/status/1114141314441011200/ph... The shorthand is that there's basically "xeon phi" and "everything else". Each of those sets has strictly increasing capabilities with each product generation - Phi Gen2 is a strict superset of Phi Gen1, but Consumer Gen2 doesn't necessarily include all the instructions in Phi Gen1. There's a few exceptions and nuances (in particular, this is generation, not chronological order), but that's really all you need to know in practice. If you want to refine that a little further, there's "consumer", "server" and "xeon phi" set and each of those is very well-ordered. Basically they just took the consumer line and added some neural network instructions to it for server. But if you're a consumer, there is only one feature set you need to worry about, and they are strictly ordered within that series. Tiger Lake will be strictly better than Ice Lake, and so on. Well, until Intel just dropped AVX-512 entirely of course, but AMD is adding support in Zen4, so it's not going away or anything. I get that people enjoy taking the piss, but there were literally 11 different "feature sets" in MMX/SSE that come up in a trivial search, and if you counted every single combination that any chip ever implemented as being a "level" there are most likely 30 or 40 "levels" in MMX/SSE. Some of those even got dropped and abandoned, others became basically mandatory for running modern software. It would be a big scary venn diagram assuming it could even be represented at all. Today we don't even think about it (except for Phenom II owners, hi guys!), we just found the useful sets of instructions and everything implements them. When was the last time you worried about whether your processor had SSE4 POPCNT? Over time it's a non-issue. AMD will implement their own subset of features in Zen4 that they think are most useful, maybe add a few of their own, and over time things will settle in exactly the same way that MMX/SSE did.