You can already use the AVX-512 instructions with vectors smaller than 512 bits; that, in fact, is one of the extensions to the base microarchitecture, and is p

You can already use the AVX-512 instructions with vectors smaller than 512 bits; that, in fact, is one of the extensions to the base microarchitecture, and is present in every desktop/server CPU that has it available (but not the original Xeon Phis, IIRC.) This is called the "Vector Length" extension. Edit: I noted you said "redesign" which is an important point. I don't disagree in principle, I just point this out to be clear you can use the new ISA with smaller vectors already, to anyone who doesn't know this. No need to throw out baby with bathwater. Maybe their "redesign" could just be ratifying this as a separate ISA feature... > drawing much power, large chip area, dragging down the clock of the entire chip The chip area thing has mostly been overblown IMO, the vector unit itself is rather large but would be anyway (you can't get away from this if you want fat vectors), and the register file is shared anyway so it's "only" 2x bigger relative to a 256b one, but still pales in comparison to the L2 or L3. The power considerations are significantly better at least as of Ice Lake/Tiger Lake, having pretty minimal impact on clock speeds/power licensing, but it's worth nothing these have only 1 FMA unit in consumer SKUs and are traditionally low core count designs. Seeing AVX-512 performance/power profiles on Sapphire Rapids or Ice Lake Xeon (dual FMAs, for one) would be more interesting but again it wouldn't match desktop SKUs in any case. It's also worth noting AVX2 has similar problems e.g. on Haswell machines where it first appeared, and would similarly cause downclocking due to thermal constraints; but at the time the blogosphere wasn't as advanced and efficient at regurgitating wives' tales with zero context or wider understanding, so you don't see it talked about as much. In any case I suspect Intel is probably thinking about moving in the direction of variable-width vector sizes. But they probably think about a lot of things. It's unclear how this will all pan out, though I do admit AVX-512 overall counts as a bit of a "fumbled bag" for them, so to speak. I just want the instructions! No bigger vectors needed.