This argument IMO is rather overblown. A quick die shot of Skylake-X indicates to me that even if you completely nerfed every AVX-512 unit appropriately (includ

This argument IMO is rather overblown. A quick die shot of Skylake-X indicates to me that even if you completely nerfed every AVX-512 unit appropriately (including the register files) on say, an 8-core or 10-core processor, you're going to get what? 1 or 2 more cores at maximum?[1] People make it sound like 70% of every Skylake-X die just sits there and you could have 50x more cores, when it's not that simple. You can delete tons of features from a modern microprocessor to save space but that isn't always the best way forward. In any case, I think this whole argument really misses another important thing, which is that the ISA and the vector width are separate here different. If Intel would just give us AVX-512 with 256b or 128b vectors, it would lead to a very big increase in use IMO, without having to have massive register files and vector data paths complicate things. The instruction set improvements are good enough to justify this IMO. (Alder Lake makes it a more complex case since they'd need to do a lot of work to unify Gracemont/Golden Cove before they could even think about that, but I still think it would be great.) They could even just half the width of the vector load/store units relative to the vector size like AMD did with Zen 2 (e.g. 256b vecs are split into 2x128b ops.) I'll still take it [1] https://twitter.com/GPUsAreMagic/status/1256866465577394181/photo/2 https://twitter.com/GPUsAreMagic/status/1256866465577394181/...