3 ms·

AVX-512 still isn't one instruction set either. It is several that are overlapping, with different feature sets. I have seen several accounts of them being ine

AVX-512 still isn't one instruction set either. It is several that are overlapping, with different feature sets. I have seen several accounts of them being inefficient (drawing much power, large chip area, dragging down the clock of the entire chip). They have also been criticised for making context switches longer. There are some good ideas in there though. What I think Intel should do is to redesign it as a single modern instruction set for 128 and 256-bit vectors (or for scalable vector lengths such as where ARM and RISC-V are going). Then express older SSE-AVX2 instructions in the new instructions' microcode, with the goal of replacing SSE-AVX2 in the long term. Otherwise, if Intel doesn't have a instruction set that is modern and feature-complete, I think Intel would be falling behind.

aseipp 5y ago
You can already use the AVX-512 instructions with vectors smaller than 512 bits; that, in fact, is one of the extensions to the base microarchitecture, and is present in every desktop/server CPU that has it available (but not the original Xeon Phis, IIRC.) This is called the "Vector Length" extension. Edit: I noted you said "redesign" which is an important point. I don't disagree in principle, I just point this out to be clear you can use the new ISA with smaller vectors already, to anyone who doesn't know this. No need to throw out baby with bathwater. Maybe their "redesign" could just be ratifying this as a separate ISA feature... > drawing much power, large chip area, dragging down the clock of the entire chip The chip area thing has mostly been overblown IMO, the vector unit itself is rather large but would be anyway (you can't get away from this if you want fat vectors), and the register file is shared anyway so it's "only" 2x bigger relative to a 256b one, but still pales in comparison to the L2 or L3. The power considerations are significantly better at least as of Ice Lake/Tiger Lake, having pretty minimal impact on clock speeds/power licensing, but it's worth nothing these have only 1 FMA unit in consumer SKUs and are traditionally low core count designs. Seeing AVX-512 performance/power profiles on Sapphire Rapids or Ice Lake Xeon (dual FMAs, for one) would be more interesting but again it wouldn't match desktop SKUs in any case. It's also worth noting AVX2 has similar problems e.g. on Haswell machines where it first appeared, and would similarly cause downclocking due to thermal constraints; but at the time the blogosphere wasn't as advanced and efficient at regurgitating wives' tales with zero context or wider understanding, so you don't see it talked about as much. In any case I suspect Intel is probably thinking about moving in the direction of variable-width vector sizes. But they probably think about a lot of things. It's unclear how this will all pan out, though I do admit AVX-512 overall counts as a bit of a "fumbled bag" for them, so to speak. I just want the instructions! No bigger vectors needed.
- moonchild 5y ago
  > "only" 2x bigger relative to a 256b one 4x bigger; avx512 has twice as many registers.
  - gpderetta 5y ago
    The number of microarchitectural registers is only loosely related to the number of architectural registers.
    - celrod 5y ago
      Skylake-X has 168 vector registers. Ice and Tiger lake have 224 The connection to the 32 micro architectural registers is quite loose.
    - moonchild 5y ago
      Granted. There is still more state to keep track of, though, and I would not be surprised if the physical register file increased in size by more than 2x.
paulmd 5y ago
people kinda oversell the complexity of the situation. like ooh big scary venn diagram right? https://twitter.com/InstLatX64/status/1114141314441011200/photo/1 https://twitter.com/InstLatX64/status/1114141314441011200/ph... The shorthand is that there's basically "xeon phi" and "everything else". Each of those sets has strictly increasing capabilities with each product generation - Phi Gen2 is a strict superset of Phi Gen1, but Consumer Gen2 doesn't necessarily include all the instructions in Phi Gen1. There's a few exceptions and nuances (in particular, this is generation, not chronological order), but that's really all you need to know in practice. If you want to refine that a little further, there's "consumer", "server" and "xeon phi" set and each of those is very well-ordered. Basically they just took the consumer line and added some neural network instructions to it for server. But if you're a consumer, there is only one feature set you need to worry about, and they are strictly ordered within that series. Tiger Lake will be strictly better than Ice Lake, and so on. Well, until Intel just dropped AVX-512 entirely of course, but AMD is adding support in Zen4, so it's not going away or anything. I get that people enjoy taking the piss, but there were literally 11 different "feature sets" in MMX/SSE that come up in a trivial search, and if you counted every single combination that any chip ever implemented as being a "level" there are most likely 30 or 40 "levels" in MMX/SSE. Some of those even got dropped and abandoned, others became basically mandatory for running modern software. It would be a big scary venn diagram assuming it could even be represented at all. Today we don't even think about it (except for Phenom II owners, hi guys!), we just found the useful sets of instructions and everything implements them. When was the last time you worried about whether your processor had SSE4 POPCNT? Over time it's a non-issue. AMD will implement their own subset of features in Zen4 that they think are most useful, maybe add a few of their own, and over time things will settle in exactly the same way that MMX/SSE did.

aseipp 5y ago

You can already use the AVX-512 instructions with vectors smaller than 512 bits; that, in fact, is one of the extensions to the base microarchitecture, and is present in every desktop/server CPU that has it available (but not the original Xeon Phis, IIRC.) This is called the "Vector Length" extension. Edit: I noted you said "redesign" which is an important point. I don't disagree in principle, I just point this out to be clear you can use the new ISA with smaller vectors already, to anyone who doesn't know this. No need to throw out baby with bathwater. Maybe their "redesign" could just be ratifying this as a separate ISA feature... > drawing much power, large chip area, dragging down the clock of the entire chip The chip area thing has mostly been overblown IMO, the vector unit itself is rather large but would be anyway (you can't get away from this if you want fat vectors), and the register file is shared anyway so it's "only" 2x bigger relative to a 256b one, but still pales in comparison to the L2 or L3. The power considerations are significantly better at least as of Ice Lake/Tiger Lake, having pretty minimal impact on clock speeds/power licensing, but it's worth nothing these have only 1 FMA unit in consumer SKUs and are traditionally low core count designs. Seeing AVX-512 performance/power profiles on Sapphire Rapids or Ice Lake Xeon (dual FMAs, for one) would be more interesting but again it wouldn't match desktop SKUs in any case. It's also worth noting AVX2 has similar problems e.g. on Haswell machines where it first appeared, and would similarly cause downclocking due to thermal constraints; but at the time the blogosphere wasn't as advanced and efficient at regurgitating wives' tales with zero context or wider understanding, so you don't see it talked about as much. In any case I suspect Intel is probably thinking about moving in the direction of variable-width vector sizes. But they probably think about a lot of things. It's unclear how this will all pan out, though I do admit AVX-512 overall counts as a bit of a "fumbled bag" for them, so to speak. I just want the instructions! No bigger vectors needed.

moonchild 5y ago
> "only" 2x bigger relative to a 256b one 4x bigger; avx512 has twice as many registers.
- gpderetta 5y ago
  The number of microarchitectural registers is only loosely related to the number of architectural registers.
  - celrod 5y ago
    Skylake-X has 168 vector registers. Ice and Tiger lake have 224 The connection to the 32 micro architectural registers is quite loose.
  - moonchild 5y ago
    Granted. There is still more state to keep track of, though, and I would not be surprised if the physical register file increased in size by more than 2x.

paulmd 5y ago

people kinda oversell the complexity of the situation. like ooh big scary venn diagram right? https://twitter.com/InstLatX64/status/1114141314441011200/photo/1 https://twitter.com/InstLatX64/status/1114141314441011200/ph... The shorthand is that there's basically "xeon phi" and "everything else". Each of those sets has strictly increasing capabilities with each product generation - Phi Gen2 is a strict superset of Phi Gen1, but Consumer Gen2 doesn't necessarily include all the instructions in Phi Gen1. There's a few exceptions and nuances (in particular, this is generation, not chronological order), but that's really all you need to know in practice. If you want to refine that a little further, there's "consumer", "server" and "xeon phi" set and each of those is very well-ordered. Basically they just took the consumer line and added some neural network instructions to it for server. But if you're a consumer, there is only one feature set you need to worry about, and they are strictly ordered within that series. Tiger Lake will be strictly better than Ice Lake, and so on. Well, until Intel just dropped AVX-512 entirely of course, but AMD is adding support in Zen4, so it's not going away or anything. I get that people enjoy taking the piss, but there were literally 11 different "feature sets" in MMX/SSE that come up in a trivial search, and if you counted every single combination that any chip ever implemented as being a "level" there are most likely 30 or 40 "levels" in MMX/SSE. Some of those even got dropped and abandoned, others became basically mandatory for running modern software. It would be a big scary venn diagram assuming it could even be represented at all. Today we don't even think about it (except for Phenom II owners, hi guys!), we just found the useful sets of instructions and everything implements them. When was the last time you worried about whether your processor had SSE4 POPCNT? Over time it's a non-issue. AMD will implement their own subset of features in Zen4 that they think are most useful, maybe add a few of their own, and over time things will settle in exactly the same way that MMX/SSE did.