Larger chips (like SoC/Application Processors) certainly have multiple such buses for bandwidth & separation-of-concerns (ie security-related stuff like bootrom

Larger chips (like SoC/Application Processors) certainly have multiple such buses for bandwidth & separation-of-concerns (ie security-related stuff like bootrom vs touchscreen controller) reasons, but I think we're far, far away from accepting the cost of extra pins just to accomodate software concerns.