3 ms·
> Compare these two videos of writing a solid block of color to the screen, first through the SPI task, and second with direct SPI hardware access: I wonder if
by a9h74j 5y ago
> Compare these two videos of writing a solid block of color to the screen, first through the SPI task, and second with direct SPI hardware access:
I wonder if the performance difference could, in some applications, create a preference for processors with enough SPI ports to dedicate one per peripheral (no chip select required). Not only no shared bus (as in I2C), but no shared SPI-task.
- AceJohnny2 5y agoLarger chips (like SoC/Application Processors) certainly have multiple such buses for bandwidth & separation-of-concerns (ie security-related stuff like bootrom vs touchscreen controller) reasons, but I think we're far, far away from accepting the cost of extra pins just to accomodate software concerns.