The interesting question is: what happens in modern out of order cores? There can be hundreds of instructions in flight, including long dependency chains of loa

The interesting question is: what happens in modern out of order cores? There can be hundreds of instructions in flight, including long dependency chains of loads. It's probably not too difficult (using cache misses) to construct a scenario where completing the currently inflight instructions might take a few microseconds. Exactly where interrupts are inserted there matters.