3 ms·
the shift register example you give would normally be synthesised to something with a synchronous clock and an async reset - during simulation the loop is waiti
by Taniwha 5y ago
the shift register example you give would normally be synthesised to something with a synchronous clock and an async reset - during simulation the loop is waiting for either
- magicalhippo 5y ago> during simulation the loop is waiting for either Ok, then we agree. Of course a simulator will have an implicit loop, that's not contentious. However you did not mention this in your initial statement, and I've read and been told explicitly not to think of it like this because there's no loop in hardware.