Do you have a pointer to Bluespec Classic (not the "modern" Bluespec)? I would make a distinction between "generator HDLs" like Verilog, Lava, Chisel, MyHDL, n

Do you have a pointer to Bluespec Classic (not the "modern" Bluespec)? I would make a distinction between "generator HDLs" like Verilog, Lava, Chisel, MyHDL, nMigen, etc and languages that actually are interpreted as logic (Verilog, Bluespec, Clash, Silice, Handel-C, ...). Yes, Verilog can do both and is a ghastly language. The former class doesn't really raise the abstraction, it just makes generators easier to write. As I've been saying for decades, I really want a language in which it is as easy to write an implementation as it is to write a [timing] software model; ideally I can use the same language for both! I know it can be done and I have been trying to scratch that itch a few times.