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No, the problem with Verilog is that it tries to be a procedural language like C when digital circuits are inherently parallel and declarative (sequential circu
by tsss 5y ago
No, the problem with Verilog is that it tries to be a procedural language like C when digital circuits are inherently parallel and declarative (sequential circuits just being special cases with feedback). VHDL is better, but still pretty bad. Learning digital circuit design on FPGAs would be so much easier if there was a well supported hardware description language that isn't stuck in the 1980s.
- gswdh 5y agoIt doesn't. Just because it shares some syntax with C does not make it 'want to be procedural'. I think that comes from the programmers bias from first learning a procedural language. I learnt C then Verilog, I am fluent in Verilog. The mindset for designing digital logic is completely different to programming computers, it literally is a completely different skill. The problem is, people think just because they can type a (procedural) programming language they can program anything that is programmed with a code which is where peoples initial distaste for Verilog and VHDL comes from. When you learn how to do it, I think designing logic is refreshing compared to writing software, there's so much baggage with software.
- tsmi 5y agoI do totally agree with the comment, and even upvoted it, but in some sense an HDL does 'want to be procedural'. For example: Procedure to make brick wall: For brick in wheel-barrow do To brick, apply mortar, place it, pound it with trowel (Apologies to all masons. I think you can tell my training is electrical engineering.) I've thought for some time that the main problem with Verilog is that it looks really close, visually, to C and that gives people the wrong impression.
- bsder 5y agoExcept that's not how you do it. My go-to example for this is the Carry-skip Adder. (https://en.wikipedia.org/wiki/Carry-skip_adder https://en.wikipedia.org/wiki/Carry-skip_adder) Things are happening simultaneously in time and space. The ripples are happening while the skips are happening. The skips go stable because the ripple goes stable or the carry will skip so the ripple has "extra time" to go stable. This is the simplest add faster than naive ripple carry. Note that it has no clocks. This is a purely combinatoric problem. And most "digital designers" will get it wrong. Hardware design is NOT software design. Good digital designers are always thinking about how to interleave things in time and space like this.
- sguav 5y agoYou have high-level-synthesis tools on many FPGA vendors tools, using C/C++ or even Python for hardware description. I personally don't think they are superior than typical HDLs, the thing that makes the difference is to think about the circuit you ought to describe, the language you use then is not as important IMHO.
- tsss 5y agoI don't mean high-level synthesis. In fact, using C++ or Python is even worse because there is even more mismatch in the abstraction.