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Very impressive. Do you have any experience with designing Verilog or SystemVerilog MIPS implementations as well? If so, how does that compare to RISC-V? Which
by chrsw 5y ago
Very impressive.
Do you have any experience with designing Verilog or SystemVerilog MIPS implementations as well? If so, how does that compare to RISC-V? Which one was easier in terms of design, testability, SoC integration and overall understandability?
- Taniwha 5y agoSorry no, I've worked on VLIW CPUs and an (unreleased) x86 core. In general though MIPS and RISCV are similar sorts of RISC architecture, they make some of the same design trade offs (no condition codes for example), RISCV avoids some of the mistakes (delay slots for example) - I'd guess they're about the same amount of work. I can imaging making a version of my CPU by switching out the instruction decoders (probably not really that simple). As far as SoC it probably doesn't matter - that's more of an issue of which internal buses you choose to use for memory and peripherals SoC stuff is probably unrelated to arcitecture -