3 ms·

Synthesizable verilog is a very small language compared to system verilog — especially in the 90s. Off the top of my head I know of six "just real quick" verilo

Synthesizable verilog is a very small language compared to system verilog — especially in the 90s. Off the top of my head I know of six "just real quick" verilog simulators that I've worked with (one of which I wrote). I'm not sure how I feel about them. On one hand, I hate dealing with licenses; on the other hand, now you've got to worry that your custom simulation matches behavior with the synthesis tools. A lot of the "nonstandard" interpretation for synthesizable verilog from the bigs comes from practical understanding of the behavior for a given node. Most of that is captured in ABC files ... but not all of it.

Taniwha 5y ago
It was more than simple synthesisable verilog, but not a lot - it was also a compiler rather than an interpreter - at the time VCS was just starting to be a thing, verilog as a language was not at all well defined (lots of assumptions about event ordering that no-one should have been making) I was designing Mac graphics accelerators I'd built it on a some similar infrastructure I'd built to capture trace from people's machines to try and figure out where QuickDraw was really spending it's time - we ended up with a minimilistic graphics accelerator that beat the pants off of everyone else
- thechao 5y ago
  This is why I think Moore (LLHD), Verilator, and Yosys are such awesome tools. They move a lot more slowly than (say) GCC, but I personally think they're all close to the tipping point.
  - Taniwha 5y ago
    I wrote a second, much more standard Verilog compiler (because by then there was a standard) with the intent of essentially selling cloud simulation time (being 3rd to a marketplace means you have to innovate) - sadly I was a bit ahead of my time ('cloud' was not yet a word) the whole California/Enron "smartest guys in the room" debacle kind of made a self financed startup like that non-viable So in the end I open sourced the compiler ('vcomp') but it didn't take off

Taniwha 5y ago

It was more than simple synthesisable verilog, but not a lot - it was also a compiler rather than an interpreter - at the time VCS was just starting to be a thing, verilog as a language was not at all well defined (lots of assumptions about event ordering that no-one should have been making) I was designing Mac graphics accelerators I'd built it on a some similar infrastructure I'd built to capture trace from people's machines to try and figure out where QuickDraw was really spending it's time - we ended up with a minimilistic graphics accelerator that beat the pants off of everyone else

thechao 5y ago
This is why I think Moore (LLHD), Verilator, and Yosys are such awesome tools. They move a lot more slowly than (say) GCC, but I personally think they're all close to the tipping point.
- Taniwha 5y ago
  I wrote a second, much more standard Verilog compiler (because by then there was a standard) with the intent of essentially selling cloud simulation time (being 3rd to a marketplace means you have to innovate) - sadly I was a bit ahead of my time ('cloud' was not yet a word) the whole California/Enron "smartest guys in the room" debacle kind of made a self financed startup like that non-viable So in the end I open sourced the compiler ('vcomp') but it didn't take off