3 ms·
This is a very ambitious project, so respect and good luck. I am wondering if the performance will pan out in practice, as it doesn't seem to have a very deep
by titzer 5y ago
This is a very ambitious project, so respect and good luck.
I am wondering if the performance will pan out in practice, as it doesn't seem to have a very deep pipeline, so getting high clockspeeds may be a challenge. In particular the 5 clock branch mispredict penalty suggest the pipeline design is fairly simple. Production CPUs live and die by the gate depth and hit/miss latency of caches and predictors. A longer pipeline is the typical answer to gate delay issues. Cache design (and register file design!) is also super subtle; L1 is extremely important.
- evilos 5y agoThey mention in their arch slides that they expect to add at least 2 more pipeline stages to hit higher clocks.
- Taniwha 5y agoAs mentioned here I expect that reality will intrude and the pipe will get bigger - of course good a BTC (and spending lots of gates on it) is important because that's what mitigates that deep pipe. I haven't published my latest work (end of the week) I have a minor bump to ~6.5 DMips/MHz - Dhrystone isn't everything but it's still proving a useful tool to tweak the architecture (which is what's going on now)