Also IANAL, but as I understand it, the HDL would compile down to a sequence of gates, and presumably we'd treat that the same way as a binary - a "Non-Source F

Also IANAL, but as I understand it, the HDL would compile down to a sequence of gates, and presumably we'd treat that the same way as a binary - a "Non-Source Form" as the GPL calls it. So anyone that receives a copy of those gates (either as a binary blob for a FPGA, or pre-flashed on a FPGA, or made on actual silicon) would be entitled to the source as per GPL3 section 6 "Conveying Non-Source Forms". I don't think the GPL anti-tivoization clause has much bearing there other than presumably you'd have to provide the full tool chain that resulted in the final gates - presumably this would affect companies producing actual chips the most since you couldn't have any propriety optimization or layout steps in producing the actual chip design, though also no DRM for FPGAs (is that even a thing?)