3 ms·

> Well... that's not necessarily true. For instance, even the cheapest 2-layer process that JLCPCB offers is capable of 0.127mm tracks spaced 0.127mm apart... w

> Well... that's not necessarily true. For instance, even the cheapest 2-layer process that JLCPCB offers is capable of 0.127mm tracks spaced 0.127mm apart... which means you can lay down tracks at a minimum of 0.254mm apart. That's good enough to connect to pads with a 0.35mm pitch. The fence post error of PCBs, you need 4x the minimum spacing / trace width to breakout without vias. 1x trace, two spaces, and half a trace on both sides to match your BGA pitch. Best you can do on JLC is a 2 row 0.5mm breakout without resorting to tricks. You really need 0.1mm capability for these tiny pitches. Edit: Just double checked JLC, their 4 layer does offer full 0.09mm capability, which is new! It use to only be the outer layers that could be 0.09mm, and 0.127 on inner layers. You can actually do a proper 0.8mm BGA breakout now, and 1mm pitch is child’s play now, you can fit two traces between vias.

Sprite_tm 5y ago
Can you elaborate that? For each BGA ball, I need one trace width of trace, plus one spacing width to the next trace, right? There's a space on the other side as well, but that's already 'provided' by the trace above. Or do you mean if you want to connect to both the outer as well as the inner layer of balls? Then you'd be right I think, but that was not what I meant; I only calculated the spacing to connect to the outer layer and nothing more.
- fps-hero 5y ago
  The best reference I can point to is the Xilinx bga pdf in google. Basically, for given capability (geometry really) there are only certain ways of breaking out pads. You can either fit multiple (luxury of process), one, or zero traces between vias and pads. And as a result of this, you need xTimes PCB layers to effectively breakout BGAs given there ball depth. Simple chip scale bgas can be broken out one layer, but the geometry requires capabilities that only multi layer process provides. The real takeaway is JLCPCB just got a whole lot more competitive with there 6 layer service. 0.2/0.4 vias, 0.1 trace/space is the holy grail. Anything smaller geometry than that you need board house support, and a finely tuned assembly process.
thrtythreeforty 5y ago
Nice, thank you for the notice about the inner layers. They don't make a big deal about it when they improve the capabilities: in the past they've also improved minimum via ring diameter from 0.45mm to 0.4mm, which doesn't sound like much but it allows you to fit the vias in between 0.8mm pads on inner layers. Patiently waiting for the day microvias become too cheap to meter.
- fps-hero 5y ago
  I wish they advertised it more! That reduction in annular pad plus the inner player geometry is a game changer. Effectively any 0.8mm pitch bga is completely prototype-able now.
  - thrtythreeforty 5y ago
    I did a 0.8mm fanout on their older limits, and it was barely doable - the inner balls of the ECP5 FPGAs are all power and ground, and with careful depopulating of the inner layers' annular rings it's possible to get enough working room to make it all fit! But if you want signals in those inner balls... still pretty tight. And the 15x15 ECP5 is the absolute max this would work for; after that you hit both needing inner layers to route on, and additional ground planes for the outer layers' return current.
mmastrac 5y ago
I tried laying out a tiny little USB switch on a JLCPCB board with .154mm traces and got about 50% mortality. Could be partly that I'm not good at PCB design but clearly there's a _lot_ of margin you need to leave.
GeorgeTirebiter 5y ago
Let me translate for USA (1 inch = 1000 mils) 0.127mm = 5 mils. Note that is it impossible to achieve +/- 0.001 mm tolerance in PCB manufacture, so including 3 digits' precision is - not helpful. 0.254 mm = 10 mils .35mm pitch = 13.78 mils (why not 14? Because on packages, with lots of pads, you'll get errors if you don't account for small fractions) 0.09mm = 3.5 mils 1 mm = 39.37 mils PCB manufacture traditionally has been done in mils, with good reason: you can use no decimal-point representations of most of the useful quantities in PCB layout. And, don't you love 100 mil, 50 mil, 2 mm, and 1 mm connectors ? Not to mention 156 mil and https://www.samtec.com/connectors/high-speed-board-to-board/ultra-micro/searay-ultra-lp https://www.samtec.com/connectors/high-speed-board-to-board/... which has 0.8 mm pitch. I soooo love connectors, if I were a Connector Manufacturer.

Sprite_tm 5y ago

Can you elaborate that? For each BGA ball, I need one trace width of trace, plus one spacing width to the next trace, right? There's a space on the other side as well, but that's already 'provided' by the trace above. Or do you mean if you want to connect to both the outer as well as the inner layer of balls? Then you'd be right I think, but that was not what I meant; I only calculated the spacing to connect to the outer layer and nothing more.

fps-hero 5y ago
The best reference I can point to is the Xilinx bga pdf in google. Basically, for given capability (geometry really) there are only certain ways of breaking out pads. You can either fit multiple (luxury of process), one, or zero traces between vias and pads. And as a result of this, you need xTimes PCB layers to effectively breakout BGAs given there ball depth. Simple chip scale bgas can be broken out one layer, but the geometry requires capabilities that only multi layer process provides. The real takeaway is JLCPCB just got a whole lot more competitive with there 6 layer service. 0.2/0.4 vias, 0.1 trace/space is the holy grail. Anything smaller geometry than that you need board house support, and a finely tuned assembly process.

thrtythreeforty 5y ago

Nice, thank you for the notice about the inner layers. They don't make a big deal about it when they improve the capabilities: in the past they've also improved minimum via ring diameter from 0.45mm to 0.4mm, which doesn't sound like much but it allows you to fit the vias in between 0.8mm pads on inner layers. Patiently waiting for the day microvias become too cheap to meter.

fps-hero 5y ago
I wish they advertised it more! That reduction in annular pad plus the inner player geometry is a game changer. Effectively any 0.8mm pitch bga is completely prototype-able now.
- thrtythreeforty 5y ago
  I did a 0.8mm fanout on their older limits, and it was barely doable - the inner balls of the ECP5 FPGAs are all power and ground, and with careful depopulating of the inner layers' annular rings it's possible to get enough working room to make it all fit! But if you want signals in those inner balls... still pretty tight. And the 15x15 ECP5 is the absolute max this would work for; after that you hit both needing inner layers to route on, and additional ground planes for the outer layers' return current.

mmastrac 5y ago

I tried laying out a tiny little USB switch on a JLCPCB board with .154mm traces and got about 50% mortality. Could be partly that I'm not good at PCB design but clearly there's a _lot_ of margin you need to leave.

GeorgeTirebiter 5y ago

Let me translate for USA (1 inch = 1000 mils) 0.127mm = 5 mils. Note that is it impossible to achieve +/- 0.001 mm tolerance in PCB manufacture, so including 3 digits' precision is - not helpful. 0.254 mm = 10 mils .35mm pitch = 13.78 mils (why not 14? Because on packages, with lots of pads, you'll get errors if you don't account for small fractions) 0.09mm = 3.5 mils 1 mm = 39.37 mils PCB manufacture traditionally has been done in mils, with good reason: you can use no decimal-point representations of most of the useful quantities in PCB layout. And, don't you love 100 mil, 50 mil, 2 mm, and 1 mm connectors ? Not to mention 156 mil and https://www.samtec.com/connectors/high-speed-board-to-board/ultra-micro/searay-ultra-lp https://www.samtec.com/connectors/high-speed-board-to-board/... which has 0.8 mm pitch. I soooo love connectors, if I were a Connector Manufacturer.