3 ms·
> In RISC-V the equivalent would require a whole 3 different instructions I'm surprised that it wasn't pointed out that this should probably be eliminated by a
by jhgb 5y ago
> In RISC-V the equivalent would require a whole 3 different instructions
I'm surprised that it wasn't pointed out that this should probably be eliminated by a compiler transformation. Rather than loading from r0+r1<<2 and incrementing r1 by one every loop iteration, surely it might be possible to load from just r0 and increment it by 4 every loop iteration?
- avianes 5y agoWe don't need indexed loads only for loops. But even within loops, you may need indexed load. One simple example: when you do loop unrolling, you must access elements n+4, n+8 and n+12 etc.
- jhgb 5y agoTrue, there are other uses. However some people seem to be pointing out that on average, the RISC-V code is still smaller on average. As for unrolling, isn't this a job for RV64V?