>The M1 has a 192k instruction cache for performance cores which is not ‘tiny’. ARMv8 and ARMv9 have poor code density. These cache are large as a workaround t

>The M1 has a 192k instruction cache for performance cores which is not ‘tiny’. ARMv8 and ARMv9 have poor code density. These cache are large as a workaround to that. This isn't free, as besides making the die larger (and thus lower yields), the L1's clock speed is limited due to its size.