3 ms·

I don't think that's a deal breaker if you're willing to lay thick interconnects, treating the connection much like you'd treat something like EMIB. After all,

I don't think that's a deal breaker if you're willing to lay thick interconnects, treating the connection much like you'd treat something like EMIB. After all, Cerebras made a functional wafer sized chip.

watersb 5y ago
> After all, Cerebras made a functional wafer sized chip. https://cerebras.net/ https://cerebras.net/ Yes, but the Cerebras wafer-chip is a repeating pattern of logic, memory, and interconnect tiles. Each pattern is well under the reticle limit of the process node they're using. And how many Cerebras wafers have shipped? I would imagine that they can afford to spend more engineering effort in the late manufacturing phase, fusing off bad bits, maybe salvaging some other bits... but enabling such late-stage functional-unit binning requires a larger mesh topography. Apple is using a design that's at the limit of economic feasibility at the mass-market sales volume they can support. They can amortize the engineering expense down among the single most popular retail item on the planet. Cerebras is an engineering marvel, but I wouldn't call it a mass-market item. The Mac Studio more closely resembles high-end IBM POWER mainframe modules. Stunning that you can just go out and buy one. And you don't need a data center to feed it. https://www.anandtech.com/show/16626/cerebras-unveils-wafer-scale-engine-two-wse2-26-trillion-transistors-100-yield https://www.anandtech.com/show/16626/cerebras-unveils-wafer-... https://cerebras.net/ https://cerebras.net/
- reitzensteinm 5y ago
  But you'd also keep each half of the M1 ultra under the limit. I'm not saying it's a good idea, because they'd have done it if it was. They clearly know what they're doing. I'm just saying that it's not an absolute blocker for a design you'd otherwise be connecting over something like EMIB anyway.
  - watersb 5y ago
    ... three days later ... Oh, I see: you are wondering why Apple M1 Ultra, as two chips linked by EMIB, couldn't just be the two chips adjacent on the wafer. See the difference? Apple knows what their yields are; if they could be sure to get two matched SoC M1 Max chips right next to one another on the wafer, they could punch that pair out and bypass the whole EMIB thing. I don't know enough about testing and dicing 100-billion-transistor chips to know how expensive that would be.

watersb 5y ago

> After all, Cerebras made a functional wafer sized chip. https://cerebras.net/ https://cerebras.net/ Yes, but the Cerebras wafer-chip is a repeating pattern of logic, memory, and interconnect tiles. Each pattern is well under the reticle limit of the process node they're using. And how many Cerebras wafers have shipped? I would imagine that they can afford to spend more engineering effort in the late manufacturing phase, fusing off bad bits, maybe salvaging some other bits... but enabling such late-stage functional-unit binning requires a larger mesh topography. Apple is using a design that's at the limit of economic feasibility at the mass-market sales volume they can support. They can amortize the engineering expense down among the single most popular retail item on the planet. Cerebras is an engineering marvel, but I wouldn't call it a mass-market item. The Mac Studio more closely resembles high-end IBM POWER mainframe modules. Stunning that you can just go out and buy one. And you don't need a data center to feed it. https://www.anandtech.com/show/16626/cerebras-unveils-wafer-scale-engine-two-wse2-26-trillion-transistors-100-yield https://www.anandtech.com/show/16626/cerebras-unveils-wafer-... https://cerebras.net/ https://cerebras.net/

reitzensteinm 5y ago
But you'd also keep each half of the M1 ultra under the limit. I'm not saying it's a good idea, because they'd have done it if it was. They clearly know what they're doing. I'm just saying that it's not an absolute blocker for a design you'd otherwise be connecting over something like EMIB anyway.
- watersb 5y ago
  ... three days later ... Oh, I see: you are wondering why Apple M1 Ultra, as two chips linked by EMIB, couldn't just be the two chips adjacent on the wafer. See the difference? Apple knows what their yields are; if they could be sure to get two matched SoC M1 Max chips right next to one another on the wafer, they could punch that pair out and bypass the whole EMIB thing. I don't know enough about testing and dicing 100-billion-transistor chips to know how expensive that would be.