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The M1 has a 192k instruction cache for performance cores which is not ‘tiny’. If there is lots of evidence for the performance benefits of improved density vs
by klelatti 5y ago
The M1 has a 192k instruction cache for performance cores which is not ‘tiny’.
If there is lots of evidence for the performance benefits of improved density vs the alternative of fixed instruction width in real world CPUs then I’m sure you’ll be able to cite it.
- snvzz 5y ago>The M1 has a 192k instruction cache for performance cores which is not ‘tiny’. ARMv8 and ARMv9 have poor code density. These cache are large as a workaround to that. This isn't free, as besides making the die larger (and thus lower yields), the L1's clock speed is limited due to its size.