4 ms·

It's generally superlinear due to yield effects - this is a bit oversimplified, but in particular, with lithography defects being more or less randomly placed t

It's generally superlinear due to yield effects - this is a bit oversimplified, but in particular, with lithography defects being more or less randomly placed throughout the wafer, a defect in a 100mm2 die impacts a far smaller percentage of the dies in the wafer than a defect in an 800mm2 die. Assuming a constant defect rate per wafer, you'll end up with drastically less usable wafer area with large dies than with small ones. This was a major reason that AMD was able to price Ryzen so aggressively even at the high end - a high-end CPU is just made of more of the same small dies used in low-end CPUs, albeit requiring a better bin, instead of having to make a much larger single die. The constant defect rate isn't typically a correct assumption across different products (e.g. different CPU or GPU dies) - different feature designs will have differing defect rates. Maybe Apple was able to design the M1 Ultra's features so that defect rate is very very low, though - I don't really know much about that silicon.

imachine1980_ 5y ago
probably this is why they decide to do it as last m1 product, in genera the more you use a process -> less error in the production process happens.
kzrdude 5y ago
This is probably M1 Ultra is designed to be two M1 Max glued together, more or less.
- addaon 5y ago
  The M1 Ultra would be at or over the reticle limit as a single die, depending on how much area could be saved by removing the inter-die transceivers.
  - reitzensteinm 5y ago
    I don't think that's a deal breaker if you're willing to lay thick interconnects, treating the connection much like you'd treat something like EMIB. After all, Cerebras made a functional wafer sized chip.
    - watersb 5y ago
      > After all, Cerebras made a functional wafer sized chip. https://cerebras.net/ https://cerebras.net/ Yes, but the Cerebras wafer-chip is a repeating pattern of logic, memory, and interconnect tiles. Each pattern is well under the reticle limit of the process node they're using. And how many Cerebras wafers have shipped? I would imagine that they can afford to spend more engineering effort in the late manufacturing phase, fusing off bad bits, maybe salvaging some other bits... but enabling such late-stage functional-unit binning requires a larger mesh topography. Apple is using a design that's at the limit of economic feasibility at the mass-market sales volume they can support. They can amortize the engineering expense down among the single most popular retail item on the planet. Cerebras is an engineering marvel, but I wouldn't call it a mass-market item. The Mac Studio more closely resembles high-end IBM POWER mainframe modules. Stunning that you can just go out and buy one. And you don't need a data center to feed it. https://www.anandtech.com/show/16626/cerebras-unveils-wafer-scale-engine-two-wse2-26-trillion-transistors-100-yield https://www.anandtech.com/show/16626/cerebras-unveils-wafer-... https://cerebras.net/ https://cerebras.net/
      - reitzensteinm 5y ago
        But you'd also keep each half of the M1 ultra under the limit. I'm not saying it's a good idea, because they'd have done it if it was. They clearly know what they're doing. I'm just saying that it's not an absolute blocker for a design you'd otherwise be connecting over something like EMIB anyway.
        watersb 5y ago
        ... three days later ... Oh, I see: you are wondering why Apple M1 Ultra, as two chips linked by EMIB, couldn't just be the two chips adjacent on the wafer. See the difference? Apple knows what their yields are; if they could be sure to get two matched SoC M1 Max chips right next to one another on the wafer, they could punch that pair out and bypass the whole EMIB thing. I don't know enough about testing and dicing 100-billion-transistor chips to know how expensive that would be.
- tuvan 5y ago
  Is it actually 2 different pieces of silicon though? I thought they were 2xM1 Max as a single silicon. Which wouldn't help with defect rates
  - addaon 5y ago
    It is two separate dice, with an EMIB-style interconnect.
    - deleted 5y ago
      [deleted]
    - mcronce 5y ago
      That makes a lot of sense. The Max is still pretty fucking big, but two of those is a lot more manageable than a single monolothic die double the size
      - ace2358 5y ago
        I just listened to the latest atp.fm podcast. I think John said that it actually is two adjacent M1 max dies. The Ultra can’t be made from two random working die. They have to physically be adjacent on the wafer. I don’t know if that means it’s physically one due though.
        wmf 5y ago
        Usually dies aren't mirrored on the wafer so I'm calling citation needed on this one.
        ace2358 5y ago
        Not sure if the counts. I know it’s a patent and it could be anything. But it talks about two adjacent dies being used if they’re good or being split if there is a defect. https://patents.google.com/patent/US20210217702A1/en?oq=2021%2f0217702 https://patents.google.com/patent/US20210217702A1/en?oq=2021...
kllrnohj 5y ago
Apple has both a 48 core & 64 core GPU variant of the M1 Ultra. Since the GPU is the largest single element of the M1 Max / Ultra, that's how they are handling yields. And it's then +$1000 for the 64 core variant over the 48 core, suggesting probably "normal" TSMC yields and then a very healthy profit margin. Apple does have the luxury of just charging whatever they want for this SoC since they are a market unto themselves. So even if yields are bad, they can just pass that cost along to the consumer. Not entirely unlike what Intel used to do with Xeons before AMD re-entered the picture and what Nvidia kinda does with the likes of the A100.

imachine1980_ 5y ago

probably this is why they decide to do it as last m1 product, in genera the more you use a process -> less error in the production process happens.

kzrdude 5y ago

This is probably M1 Ultra is designed to be two M1 Max glued together, more or less.

addaon 5y ago
The M1 Ultra would be at or over the reticle limit as a single die, depending on how much area could be saved by removing the inter-die transceivers.
- reitzensteinm 5y ago
  I don't think that's a deal breaker if you're willing to lay thick interconnects, treating the connection much like you'd treat something like EMIB. After all, Cerebras made a functional wafer sized chip.
  - watersb 5y ago
    > After all, Cerebras made a functional wafer sized chip. https://cerebras.net/ https://cerebras.net/ Yes, but the Cerebras wafer-chip is a repeating pattern of logic, memory, and interconnect tiles. Each pattern is well under the reticle limit of the process node they're using. And how many Cerebras wafers have shipped? I would imagine that they can afford to spend more engineering effort in the late manufacturing phase, fusing off bad bits, maybe salvaging some other bits... but enabling such late-stage functional-unit binning requires a larger mesh topography. Apple is using a design that's at the limit of economic feasibility at the mass-market sales volume they can support. They can amortize the engineering expense down among the single most popular retail item on the planet. Cerebras is an engineering marvel, but I wouldn't call it a mass-market item. The Mac Studio more closely resembles high-end IBM POWER mainframe modules. Stunning that you can just go out and buy one. And you don't need a data center to feed it. https://www.anandtech.com/show/16626/cerebras-unveils-wafer-scale-engine-two-wse2-26-trillion-transistors-100-yield https://www.anandtech.com/show/16626/cerebras-unveils-wafer-... https://cerebras.net/ https://cerebras.net/
    - reitzensteinm 5y ago
      But you'd also keep each half of the M1 ultra under the limit. I'm not saying it's a good idea, because they'd have done it if it was. They clearly know what they're doing. I'm just saying that it's not an absolute blocker for a design you'd otherwise be connecting over something like EMIB anyway.
      - watersb 5y ago
        ... three days later ... Oh, I see: you are wondering why Apple M1 Ultra, as two chips linked by EMIB, couldn't just be the two chips adjacent on the wafer. See the difference? Apple knows what their yields are; if they could be sure to get two matched SoC M1 Max chips right next to one another on the wafer, they could punch that pair out and bypass the whole EMIB thing. I don't know enough about testing and dicing 100-billion-transistor chips to know how expensive that would be.
tuvan 5y ago
Is it actually 2 different pieces of silicon though? I thought they were 2xM1 Max as a single silicon. Which wouldn't help with defect rates
- addaon 5y ago
  It is two separate dice, with an EMIB-style interconnect.
  - deleted 5y ago
    [deleted]
  - mcronce 5y ago
    That makes a lot of sense. The Max is still pretty fucking big, but two of those is a lot more manageable than a single monolothic die double the size
    - ace2358 5y ago
      I just listened to the latest atp.fm podcast. I think John said that it actually is two adjacent M1 max dies. The Ultra can’t be made from two random working die. They have to physically be adjacent on the wafer. I don’t know if that means it’s physically one due though.
      - wmf 5y ago
        Usually dies aren't mirrored on the wafer so I'm calling citation needed on this one.
        ace2358 5y ago
        Not sure if the counts. I know it’s a patent and it could be anything. But it talks about two adjacent dies being used if they’re good or being split if there is a defect. https://patents.google.com/patent/US20210217702A1/en?oq=2021%2f0217702 https://patents.google.com/patent/US20210217702A1/en?oq=2021...

kllrnohj 5y ago

Apple has both a 48 core & 64 core GPU variant of the M1 Ultra. Since the GPU is the largest single element of the M1 Max / Ultra, that's how they are handling yields. And it's then +$1000 for the 64 core variant over the 48 core, suggesting probably "normal" TSMC yields and then a very healthy profit margin. Apple does have the luxury of just charging whatever they want for this SoC since they are a market unto themselves. So even if yields are bad, they can just pass that cost along to the consumer. Not entirely unlike what Intel used to do with Xeons before AMD re-entered the picture and what Nvidia kinda does with the likes of the A100.