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The strategy of creating a large die with lots of execution units, then running the chip at a lower clock speed for power efficiency has been Apple's way of doi
by GeekyBear 5y ago
The strategy of creating a large die with lots of execution units, then running the chip at a lower clock speed for power efficiency has been Apple's way of doing things for a while now.
>Apple has built a wide enough GPU that they can keep clockspeeds nice and low on the voltage/frequency curve, which keeps overall power consumption down. The RTX 3090, by contrast, is designed to chase performance with no regard to power consumption, allowing NVIDIA to get great performance out of it, but only by riding high on the voltage frequency curve.
https://www.anandtech.com/show/17306/apple-announces-m1-ultra-combining-two-m1-maxes-for-even-more-performance https://www.anandtech.com/show/17306/apple-announces-m1-ultr...
This strategy is something that Anandtech's been calling out since the iPhone 5s chip.
>Brian and I have long been hinting at the sort of ridiculous frequency/voltage combinations mobile SoC vendors have been shipping at for nothing more than marketing purposes. I remember ARM telling me the ideal target for a Cortex A15 core in a smartphone was 1.2GHz. Samsung’s Exynos 5410 stuck four Cortex A15s in a phone with a max clock of 1.6GHz. The 5420 increases that to 1.7GHz. The problem with frequency scaling alone is that it typically comes at the price of higher voltage. There’s a quadratic relationship between voltage and power consumption, so it’s quite possibly one of the worst ways to get more performance.
https://www.anandtech.com/show/7335/the-iphone-5s-review/2 https://www.anandtech.com/show/7335/the-iphone-5s-review/2
- mikhailt 5y ago> The strategy of creating a large die with lots of execution units, then running the chip at a lower clock speed for power efficiency has been Apple's way of doing things for a while now. > This strategy is something that Anandtech's been calling out since the iPhone 5s chip. Not sure that applies to M1 Ultra that's clearly marketed as a desktop SoC, not a mobile device or laptop SoC. Optimizing for energy efficiency or battery life is not the same as optimizing for performance first, which is what M1 Ultra is designed for. Not to mention, there's a reason Windows and Linux have multiple power profiles that changes how schedulers and power loads work. macOS has "high power mode" for m1 on laptops and yet strangely, it is not even available on the Mac Studio. Keep in mind that Apple showed a graph that clearly shows the GPU was at 100-110w. Why do that if they won't run it at that wattage or even talk about 3090 in the first place? Why ruin their reputation over a silly little thing? Everyone on the planet will easily debunk that. Also, why even bother adding a high-quality cooling system that the Mac Studio clearly don't need since both CPU/GPU are going to be capped at lower power wattage? We'll find out eventually one way or another.
- GeekyBear 5y ago> Not sure that applies to M1 Ultra that's clearly marketed as a desktop SoC, not a mobile device or laptop SoC. The M1 Ultra is using the same CPU cores and GPU cores as an iPhone, just more of them. It's long been their strategy across the board. Throw silicon die area at tons of execution units and run the chip at a lower clock speed for power efficiency. For example, the 2012 A5X iPad chip had about the same die area as 4 core Ivy Bridge, which was huge for a mobile device SOC. https://www.anandtech.com/show/6330/the-iphone-5-review/4 https://www.anandtech.com/show/6330/the-iphone-5-review/4 Since they are selling the whole widget, they aren't as dependent on minimizing die area to maximize their profit margin.
- addaon 5y ago> The M1 Ultra is using the same CPU cores and GPU cores as an iPhone, just more of them. Not only that, but it's running them at basically the same clock speeds as the rest of the M1 family, and even as the iPhone. This suggests that they're running at not far above a best efficiency point, rather than way past the elbow of the voltage curve as is traditional for desktop chips.
- jleahy 5y agoI would have thought this approach would cause issues for leakage power? Better to run fast then sleep and power gate to cut leakage, especially at smaller geometries. Or do you think they are mostly using HVt cells?
- GeekyBear 5y agoDoesn't power leakage get much, much worse as temperature increases?
- jleahy 5y agoYes it does, but that just means you want to use as little power as possible (which is presumably already the case). That effect is actually so bad that I have previously experienced thermal runaway due to it (more power => higher temperature => more power => …)