In a recent conference talk by John Shalf in Stockholm (see http://neuroinformatics2008.org/program-new/workshops/future-hardware-challenges/future-hardware-cha

In a recent conference talk by John Shalf in Stockholm (see http://neuroinformatics2008.org/program-new/workshops/future-hardware-challenges/future-hardware-challenges-to-scientific-computing#john-shalf http://neuroinformatics2008.org/program-new/workshops/future... ), the monster was set on the table: chip companies are simplifying chips by reducing their clock speed (thus removing lots of now superfluous prebuffering and synchronization adjacent electronics) and tiling them to the hundreds and even thousands. We are not far away from the 10,000 core chip. Say 3 years? Very hard to guess. An important point of the talk: he explained how the chip industry ignored accademia as long as it could just increase clock speed to achieve better performance. But now, in the parallelization mess, they are comming back for ideas on how to make efficient use of the cores for compilers (which, according to John, are currently failing at exploiting multicores) and for software in general. [John calls this situation the "manycore", as opposed to the current "multicore"]