> - I thought ARM32 has 12(-14) usable registers (compared to 14-15 in x86-64), so why these mentions of "scarce Cortex-M0+ registers"? Cortex-M0+ is thumb-onl

> - I thought ARM32 has 12(-14) usable registers (compared to 14-15 in x86-64), so why these mentions of "scarce Cortex-M0+ registers"? Cortex-M0+ is thumb-only (compressed 16bit instruction encoding). "In Thumb state, the high registers, r8-r15, are not part of the standard register set. The assembly language programmer has limited access to them, but can use them for fast temporary storage." > (Does FIQ mode reduce the number of usable registers?) There is no FIQ mode in Cortex-M. Instead you usually have the nifty Nested Vectored Interrupt Controller (NVIC) and it is designed so your interrupt handlers can be regular C functions, with no special handling needed (no special interrupt return instruction) needed.