4 ms·

This is impressive. I'm wondering about a few things: - "I decided to leave the XIP cache to do its thing, and select a few small areas of hot code or data to

This is impressive. I'm wondering about a few things: - "I decided to leave the XIP cache to do its thing, and select a few small areas of hot code or data to promote to RAM manually"[1]: I understood this as you leaving the XIP cache activated. But this seems at odds with "16K of flash XIP cache, that we’ve talked about, but decided not to use."[also 1], which I'm interpreting as "decided not to make use of the XIP cache (i.e. turn it off)" (maybe I'm misreading). - I thought ARM32 has 12(-14) usable registers (compared to 14-15 in x86-64), so why these mentions of "scarce Cortex-M0+ registers"? (Does FIQ mode reduce the number of usable registers?) - "not good on a Cortex M0+ where the overhead of a function call is generally 30-40 cycles, with the corresponding loss of most of your precious “in-register” state": are function calls disproportionally slower on Cortex M0+? (Certainly 30-40 cycles seems high.) Why is that? (Registers r4-r11 are callee-saved[2], thus not lost; mutable data might have to be re-read from memory, though--just like on other architectures, but maybe CPU caches are faster on those.) - "These OR values can be stored in a lookup table indexed by higher bits in the sample position, and thus the 8x space savings can be realized without needing any branches in the code!"[3]: Cortex-M0+ has a 2-stage pipeline[4], I'd hence expect the cost of a jump to be just 1 additional cycle, for the re-processing of the 1st stage for the next instruction (maybe I'm wrong), which would be the same as a memory access. (Maybe multiple jumps can be saved this way, though.) Did measurements show the lookup table to be faster? [1] https://kilograham.github.io/rp2040-doom/speed_and_ram.html https://kilograham.github.io/rp2040-doom/speed_and_ram.html [2] https://en.wikipedia.org/wiki/Calling_convention#ARM_(A32) https://en.wikipedia.org/wiki/Calling_convention#ARM_(A32) [3] https://kilograham.github.io/rp2040-doom/sound.html https://kilograham.github.io/rp2040-doom/sound.html [4] https://en.wikipedia.org/wiki/Cortex-M0%2B#Cortex-M0+ https://en.wikipedia.org/wiki/Cortex-M0%2B#Cortex-M0+

moefh 5y ago
> - "I decided to leave the XIP cache to do its thing, and select a few small areas of hot code or data to promote to RAM manually"[1]: I understood this as you leaving the XIP cache activated. But this seems at odds with "16K of flash XIP cache, that we’ve talked about, but decided not to use."[also 1], which I'm interpreting as "decided not to make use of the XIP cache (i.e. turn it off)" (maybe I'm misreading). The way I'm reading it, you can disable the XIP cache and use that 16KB of RAM for anything else you want. But the author "decided not to use" it for something else, that is, the 16KB are still being used as cache.
ranma42 5y ago
> - I thought ARM32 has 12(-14) usable registers (compared to 14-15 in x86-64), so why these mentions of "scarce Cortex-M0+ registers"? Cortex-M0+ is thumb-only (compressed 16bit instruction encoding). "In Thumb state, the high registers, r8-r15, are not part of the standard register set. The assembly language programmer has limited access to them, but can use them for fast temporary storage." > (Does FIQ mode reduce the number of usable registers?) There is no FIQ mode in Cortex-M. Instead you usually have the nifty Nested Vectored Interrupt Controller (NVIC) and it is designed so your interrupt handlers can be regular C functions, with no special handling needed (no special interrupt return instruction) needed.
- ant6n 5y ago
  In thumb2 virtually all arm32 Instructions are available, some as 32bit encodings. But even the 16bit encodings include some instructions that work on hi registers.

moefh 5y ago

> - "I decided to leave the XIP cache to do its thing, and select a few small areas of hot code or data to promote to RAM manually"[1]: I understood this as you leaving the XIP cache activated. But this seems at odds with "16K of flash XIP cache, that we’ve talked about, but decided not to use."[also 1], which I'm interpreting as "decided not to make use of the XIP cache (i.e. turn it off)" (maybe I'm misreading). The way I'm reading it, you can disable the XIP cache and use that 16KB of RAM for anything else you want. But the author "decided not to use" it for something else, that is, the 16KB are still being used as cache.

ranma42 5y ago

> - I thought ARM32 has 12(-14) usable registers (compared to 14-15 in x86-64), so why these mentions of "scarce Cortex-M0+ registers"? Cortex-M0+ is thumb-only (compressed 16bit instruction encoding). "In Thumb state, the high registers, r8-r15, are not part of the standard register set. The assembly language programmer has limited access to them, but can use them for fast temporary storage." > (Does FIQ mode reduce the number of usable registers?) There is no FIQ mode in Cortex-M. Instead you usually have the nifty Nested Vectored Interrupt Controller (NVIC) and it is designed so your interrupt handlers can be regular C functions, with no special handling needed (no special interrupt return instruction) needed.

ant6n 5y ago
In thumb2 virtually all arm32 Instructions are available, some as 32bit encodings. But even the 16bit encodings include some instructions that work on hi registers.