5 ms·

Side question but I'm curious if anyone knows, where are we heading with this constant decrease in nm for chip manufacturing processes? When will we hit a wall

by dom96 5y ago

Side question but I'm curious if anyone knows, where are we heading with this constant decrease in nm for chip manufacturing processes? When will we hit a wall and where will gains in performance come from then?

monocasa 5y ago
Like most curves that looked like exponentials initially, Moore's law turned out to be an s curve. We're already on the top half of that curve where gains are increasingly more difficult and increasingly spread out over time. There's still a more or less direct road map for another five or so full nodes, and we'll probably come up with some cute way to increase density in other ways.
barbacoa 5y ago
>When will we hit a wall and where will gains in performance come from then? nm notation used to mean the width of the smallest feature that could be made. Even today there are processes such as atomic layer deposition (ALD) that allows singular atom thick features. The difference between nodes now are in shrinking macro features, you don't necessarily make them smaller, more important is density. This is currently done with 3d transistors (finfet) and perhaps in the future going full vertical. When all other optimization have been exhausted it's likely to see multiple layers of stacked transistors simulator to what they are doing with NAND memory chips. Eventually even that will hit a wall due to thermal limitations. Beyond that people have proposed using carbonnano tube transistors. That tech is very early but has been proved to function in labs. If we ever figure out how to manufacture carbon nanotubes chips, it will be truly revolutionary; you could expect at least another 50 years of semiconductor innovation.
- sharikous 5y ago
  > If we ever figure out how to manufacture carbon nanotubes chips That's the problem. We can't. All those technologies are in such a primordial state, if at all, that we don't even know if we will ever be able to use them efficiently 20 years from now.
- whazor 5y ago
  Besides shrinking and increasing size chips, there is another big problem that might cause us to hit the wall. When the transistor count increases, it also increases the amount of effort. This is a big problem because chips need to be profitable. Although if you just shrink the chips and keep the transistor count the same, then you have a more energy efficient chip. Which is especially useful for portable devices.
sharikous 5y ago
We have already hit the wall. Decreases have been minimal, and came with a high cost. The numbers you hear about "7 nm", "5 nm", etc.. are just false. They do not represent anything real. The real numbers have been around 20 nm for a decade. They decreased a bit with Intel's competitors achieving better lithography than them before them. And we are in the realm of tons of little tricks that improve density and performance - nothing really dramatic but there are still improvements here and there. The tens of billions of dollars thrown at research achieved them but it is not comparable to the good old days of the '80s, '90s and the '00s
- paulmd 5y ago
  Yes, to emphasize: "nm" marketing is just marketing. There is no dimension on a 5nm chip that is actually 5nm. It used to represent gate length and half-pitch but that stopped being true about 20 years ago and officially became nonsense about 10 years ago, it's "what size planar node do we think these features would perform like" now. Because it's all subjective now, companies went wild with marketing, because consumers know "lower nm => better". But, say, GF 14nm is much more comparable to Intel 22nm, and GF 12nm is still solidly behind late-gen 14++, probably more comparable to TSMC 16nm. Generally Intel has been the most faithful to the "original" ratings, while TSMC has stretched it a little, and GF/IBM and Samsung have been pretty deceptive with their namings. Intel finally threw in the towel a year or so ago and moved to align their names with TSMC, "10nm ESF" is now "Intel 7" (note: no nm) and is roughly comparable with TSMC 7nm (seems like higher clocks at the top/worse efficiency at the bottom but broadly similar), and they will maintain TSMC-comparable node names going forward. Anyway, to answer OP's question directly though, "what comes after 1nm" is angstroms. You'll see node names like *90A or whatever, even though that continues to be completely ridiculous in terms of the actual node measurements.
  - corey_moncure 5y ago
    900 angstroms = 90 nanometers
    - akmarinov 5y ago
querulous 5y ago
nm is purely a marketing term and has been for 10 years or 25 years depending on what you think it measures future improvement is going to come from the same place it mostly comes from now: better design that unlocks better density and a revolutionary new litho process that as of yet doesn't exist
jasonwatkinspdx 5y ago
No one has a crystal ball, but here's the industry road map: https://irds.ieee.org/editions/2021 https://irds.ieee.org/editions/2021 (start with executive summary). TL;DR: things get really murky after a notional 2.1nm generation. Past that we'll need a new generation of EUV sources, advancements in materials, etc, that AFAIK are still quite far from certain (but I am not an expert on this stuff by any means). I personally think we're headed to a stall for a while where innovation will focus mostly on larger packaging/aggregation structures. Chiplets and related are definitely here to stay. DRAM is moving in package. Startups are playing around with ideas like wafer scale multiprocessors or ssds. I think clever combinations of engineering at this level will keep us with momentum for a while.

by dom96 5y ago

monocasa 5y ago

Like most curves that looked like exponentials initially, Moore's law turned out to be an s curve. We're already on the top half of that curve where gains are increasingly more difficult and increasingly spread out over time. There's still a more or less direct road map for another five or so full nodes, and we'll probably come up with some cute way to increase density in other ways.

barbacoa 5y ago

>When will we hit a wall and where will gains in performance come from then? nm notation used to mean the width of the smallest feature that could be made. Even today there are processes such as atomic layer deposition (ALD) that allows singular atom thick features. The difference between nodes now are in shrinking macro features, you don't necessarily make them smaller, more important is density. This is currently done with 3d transistors (finfet) and perhaps in the future going full vertical. When all other optimization have been exhausted it's likely to see multiple layers of stacked transistors simulator to what they are doing with NAND memory chips. Eventually even that will hit a wall due to thermal limitations. Beyond that people have proposed using carbonnano tube transistors. That tech is very early but has been proved to function in labs. If we ever figure out how to manufacture carbon nanotubes chips, it will be truly revolutionary; you could expect at least another 50 years of semiconductor innovation.

sharikous 5y ago
> If we ever figure out how to manufacture carbon nanotubes chips That's the problem. We can't. All those technologies are in such a primordial state, if at all, that we don't even know if we will ever be able to use them efficiently 20 years from now.
whazor 5y ago
Besides shrinking and increasing size chips, there is another big problem that might cause us to hit the wall. When the transistor count increases, it also increases the amount of effort. This is a big problem because chips need to be profitable. Although if you just shrink the chips and keep the transistor count the same, then you have a more energy efficient chip. Which is especially useful for portable devices.

sharikous 5y ago

We have already hit the wall. Decreases have been minimal, and came with a high cost. The numbers you hear about "7 nm", "5 nm", etc.. are just false. They do not represent anything real. The real numbers have been around 20 nm for a decade. They decreased a bit with Intel's competitors achieving better lithography than them before them. And we are in the realm of tons of little tricks that improve density and performance - nothing really dramatic but there are still improvements here and there. The tens of billions of dollars thrown at research achieved them but it is not comparable to the good old days of the '80s, '90s and the '00s

paulmd 5y ago
Yes, to emphasize: "nm" marketing is just marketing. There is no dimension on a 5nm chip that is actually 5nm. It used to represent gate length and half-pitch but that stopped being true about 20 years ago and officially became nonsense about 10 years ago, it's "what size planar node do we think these features would perform like" now. Because it's all subjective now, companies went wild with marketing, because consumers know "lower nm => better". But, say, GF 14nm is much more comparable to Intel 22nm, and GF 12nm is still solidly behind late-gen 14++, probably more comparable to TSMC 16nm. Generally Intel has been the most faithful to the "original" ratings, while TSMC has stretched it a little, and GF/IBM and Samsung have been pretty deceptive with their namings. Intel finally threw in the towel a year or so ago and moved to align their names with TSMC, "10nm ESF" is now "Intel 7" (note: no nm) and is roughly comparable with TSMC 7nm (seems like higher clocks at the top/worse efficiency at the bottom but broadly similar), and they will maintain TSMC-comparable node names going forward. Anyway, to answer OP's question directly though, "what comes after 1nm" is angstroms. You'll see node names like *90A or whatever, even though that continues to be completely ridiculous in terms of the actual node measurements.
- corey_moncure 5y ago
  900 angstroms = 90 nanometers
  - akmarinov 5y ago

querulous 5y ago

nm is purely a marketing term and has been for 10 years or 25 years depending on what you think it measures future improvement is going to come from the same place it mostly comes from now: better design that unlocks better density and a revolutionary new litho process that as of yet doesn't exist

jasonwatkinspdx 5y ago

No one has a crystal ball, but here's the industry road map: https://irds.ieee.org/editions/2021 https://irds.ieee.org/editions/2021 (start with executive summary). TL;DR: things get really murky after a notional 2.1nm generation. Past that we'll need a new generation of EUV sources, advancements in materials, etc, that AFAIK are still quite far from certain (but I am not an expert on this stuff by any means). I personally think we're headed to a stall for a while where innovation will focus mostly on larger packaging/aggregation structures. Chiplets and related are definitely here to stay. DRAM is moving in package. Startups are playing around with ideas like wafer scale multiprocessors or ssds. I think clever combinations of engineering at this level will keep us with momentum for a while.