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I don't get this: > Second, the recourse to two M1 Max chips fused into a M1 Ultra means TSMC’s 5 nm process has reached its upper limit. It also means TSMC’s

by genmon 5y ago

I don't get this: > Second, the recourse to two M1 Max chips fused into a M1 Ultra means TSMC’s 5 nm process has reached its upper limit. It also means TSMC’s 3 nm process isn’t ready, probably not shipping until late 2022. Apple, by virtue of their tight partnership with TSMC has known about and taken precautions against the 3 nm schedule, hence the initially undisclosed M1 Max UltraFusion design wrinkle, likely an early 2021 decision. "recourse"... "design wrinkle"... wouldn't something like UltraFusion be an architectural goal at the outset, rather than something grafted on later? Feels pretty fundamental. I have a vague memory that AMD has/had something similar -- the idea what their entire range would be the same basic core, fused together into larger and larger configurations. Seems like a smart move to concentrate engineering effort. But chip design not even slightly my area.

rayiner 5y ago
Depends on what the UltraFusion interconnect is. Ganging up chips as am unplanned stop-gap isn’t unheard of (e.g. the ATI Rage Fury Max). But it’s much harder to do when you’re talking about grafting on a cache coherent interconnect. If they’re using something off the shelf like CXL maybe it wasn’t planned from the outset.
- monocasa 5y ago
  It wasn't unplanned. The work by marcan on asahi Linux revealed support for multi die configurations baked into the M1 Max. > While working on AIC2 we discovered an interesting feature… while macOS only uses one set of IRQ control registers, there was indeed a full second set, unused and apparently unconnected to any hardware. Poking around, we found that it was indeed a fully working second half of the interrupt controller, and that interrupts delivered from it popped up with a magic “1” in a field of the event number, which had always been “0” previously. Yes, this is the much-rumored multi-die support. The M1 Max SoC has, by all appearances, been designed to support products with two of them in a multi-die module. While no such products exist yet, we’re introducing multi-die support to our AIC2 driver ahead of time. If we get lucky and there are no critical bugs, that should mean that Linux just works on those new 2-die machines, once they are released! https://asahilinux.org/2021/12/progress-report-oct-nov-2021/ https://asahilinux.org/2021/12/progress-report-oct-nov-2021/
infinityio 5y ago
> I have a vague memory that AMD has/had something similar You are correct - AMD CPUs from 2016 onwards make use of a collection of up-to-8-core chiplets linked by what they call "Infinity Fabric"
reitzensteinm 5y ago
It's possible that this product was intended to be based on M2, but support for multi die M1 was built in from the start as a hedge to avoid the kind of stagnation Intel has seen, where a node delay means they can't ship products. I'm not saying that's what happened, but it's a charitable reading of the original post.

by genmon 5y ago

rayiner 5y ago

Depends on what the UltraFusion interconnect is. Ganging up chips as am unplanned stop-gap isn’t unheard of (e.g. the ATI Rage Fury Max). But it’s much harder to do when you’re talking about grafting on a cache coherent interconnect. If they’re using something off the shelf like CXL maybe it wasn’t planned from the outset.

monocasa 5y ago
It wasn't unplanned. The work by marcan on asahi Linux revealed support for multi die configurations baked into the M1 Max. > While working on AIC2 we discovered an interesting feature… while macOS only uses one set of IRQ control registers, there was indeed a full second set, unused and apparently unconnected to any hardware. Poking around, we found that it was indeed a fully working second half of the interrupt controller, and that interrupts delivered from it popped up with a magic “1” in a field of the event number, which had always been “0” previously. Yes, this is the much-rumored multi-die support. The M1 Max SoC has, by all appearances, been designed to support products with two of them in a multi-die module. While no such products exist yet, we’re introducing multi-die support to our AIC2 driver ahead of time. If we get lucky and there are no critical bugs, that should mean that Linux just works on those new 2-die machines, once they are released! https://asahilinux.org/2021/12/progress-report-oct-nov-2021/ https://asahilinux.org/2021/12/progress-report-oct-nov-2021/

infinityio 5y ago

> I have a vague memory that AMD has/had something similar You are correct - AMD CPUs from 2016 onwards make use of a collection of up-to-8-core chiplets linked by what they call "Infinity Fabric"

reitzensteinm 5y ago

It's possible that this product was intended to be based on M2, but support for multi die M1 was built in from the start as a hedge to avoid the kind of stagnation Intel has seen, where a node delay means they can't ship products. I'm not saying that's what happened, but it's a charitable reading of the original post.