If anyone else is curious, like I was, about what the signal bus is like on the pins, and couldn't find much detail on the website, the person behind this expla

If anyone else is curious, like I was, about what the signal bus is like on the pins, and couldn't find much detail on the website, the person behind this explained a bit on the reddit AMA someone linked: https://old.reddit.com/r/linux/comments/ta85ql/my_small_modular_pc_running_linux_updated_demo/hzz84c7/ https://old.reddit.com/r/linux/comments/ta85ql/my_small_modu... So it seems like it's kind of like low-pin-count ISA-ish bus with direct pin connections to the cpu's pins. Presumably that limits how big a board you can have to the number of gpio pins you've got, or you'd have to build some kind of multiplexing like oldschool irq/port sharing... I'm really curious if it would be possible to do this as, essentially, single lane PCIe blocks instead. I think it would be harder from a hobby-project perspective (and also probably complexify the blocks), but PCIe is kind of built around flexible topologies so you could build it around a pcie root complex/switch instead of just directly exposing pins to the devices ISA-style.