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So in that one, you've got a 20-thread Intel part (6+8C/20T) at probably 3.5 GHz going against a 10-thread Apple part (8+2C/10T), at probably 3 GHz, and the App
by paulmd 5y ago
So in that one, you've got a 20-thread Intel part (6+8C/20T) at probably 3.5 GHz going against a 10-thread Apple part (8+2C/10T), at probably 3 GHz, and the Apple part still comes out on top by ~5% in Cinebench R23 MT. And that's with Intel having 50% more high-performance threads available.
Work out the IPC there - the Intel has a 2x thread count advantage, a 17% clock advantage, and Apple comes out 5% ahead. So the IPC gap there is about 2.46x.
It's not a perfect comparison of course, since we're mixing SMT and big/little cores, but in basically every area Intel should (on paper) have more resources available and Apple is coming out on top anyway by sheer IPC.
That's what I'm saying - you can't really do that approach with x86. It's not power-advantageous or transistor-advantageous to go super wide on the decode or reorder buffer like that on x86. And regardless of the tricks x86 uses to mitigate it, you've still got a 2.5x IPC gap at the end of the day. A 2.5x IPC gap will not be closed up by just a single node shrink.
And that's looking at MT, where your task scales perfectly. See where I'm going with this? Intel is using 2x the number of threads, and 3x the number of efficiency cores to get there. Apple can deliver that punch across a much lower number of threads - meaning ST-bottlenecked tasks will scale much much better on Apple.
With a single-threaded test, the M1 is pulling 7W vs 33W for the Alder Lake intel. Obviously that tells us nothing about efficiency, since we'd need to know the scores, but that's the downside, is for normal, poorly-threaded tasks, like surfing the web or editing code, the 12900HK is going to be boosting high to reach the same performance levels the M1 does at 3 GHz. And that's exactly what you see in the power figures there.
In short: you will likely see x86 able to keep up in one metric or another. You can win on performance if you just go nuclear on power. You can match on power on perfectly-threadable tasks that allow the x86 to deploy twice the threads (sharing instruction cache/etc). You can match on single-threaded battery life if you accept lesser performance. But the overall performance of the M1 derives from the massive IPC it generates, and that's something that x86 can't match nearly as easily.
Going ham on a single metric just to claim victory isn't nearly the same thing as the level of all-round performance and efficiency that Apple has achieved there.
(see also, putting a 128-thread Threadripper 3990WX workstation up against a 10-thread M1 Max laptop just to win at rendering... and people here thought that disproved that Apple was great hardware lol)
- EvgeniyZh 5y agoHow much little cores and HT contribute at this workload tho? If I say turn them off, could I claim the opposite, losing even 20% but using 40% less threads?
- atq2119 5y agoI don't think there's anything specifically different about the reorder buffer between x86 and ARM. The reorder buffer size is just a logical consequence of the frontend width. And yes, scaling an Aarch64 frontend is dead simple compared to x86 due to the fixed instruction width. The disadvantage of x86 is serious, but I don't know if we can count it out quite yet. This is the first time Intel and AMD got any serious pressure on that front. I'm sure they're taking the challenge seriously, and it'll take some years before we'll see the results.
- sroussey 5y agox86 and ARM have different memory access assumptions which affects the reorder buffer in material ways. Apple added something to their chips to use the x86 memory model when flagged for Rosseta2.