For the simplicity of this discussion let's just focus on companies selling physical chiplets. Assuming the company follows normal manufacturing processes (and

For the simplicity of this discussion let's just focus on companies selling physical chiplets. Assuming the company follows normal manufacturing processes (and assuming that company is "fabless" then this is a pretty safe assumption) then there is no risk of mixing different silicon from different vendors/fabs in a single package. This is being done today. Currently designers do have to take into account mixing parts that were designed for various package technologies. If a chip was designed for "flip-chp" and another chip for "wire-bond" then putting them both in the same package might require some different packaging techniques... That said - I'd assume if a company was going to build a chip and specifically market it for this new UCIe standard then they'd probably target a WLCSP type final process which is fairly common today. https://amkor.com/packaging/wafer-level-packaging/wlcsp/ https://amkor.com/packaging/wafer-level-packaging/wlcsp/