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Is there any point in standardizing on an industry-wide interconnect when it seems unlikely that there will ever be a multi-chiplet module which includes compon

Is there any point in standardizing on an industry-wide interconnect when it seems unlikely that there will ever be a multi-chiplet module which includes components from multiple vendors? It seems like interconnects are something you'd want to make as fast as possible in order to stay competitive. Standardizing on a technology not controlled by your company is likely to slow down your innovation. At best, this seems like a helping hand to smaller companies like Marvell which might not have the resources to design a competitive interconnect solution themselves.

halJordan 5y ago
Your premise that it it is unlikely that there will be multi-vendor chiplets on a single chip is undermined by the industry coming together and creating a standard to use each other’s chiplets in a single chip.
kijiki 5y ago
https://ark.intel.com/content/www/us/en/ark/products/130409/intel-core-i78809g-processor-with-radeon-rx-vega-m-gh-graphics-8m-cache-up-to-4-20-ghz.html https://ark.intel.com/content/www/us/en/ark/products/130409/... Intel has already shipped a MCM with an Intel CPU and a AMD GPU, back in 2018. That probably just used PCIe, since cache coherence wasn't needed.
paulgerhardt 5y ago
The move to standardize the interposer was driven by DARPA to get Raytheon imaging chips working with Intel AI chips. See slide 109: https://www.darpa.mil/attachments/ERI-DAProposersDay_ConsolidatedSlides.pdf https://www.darpa.mil/attachments/ERI-DAProposersDay_Consoli...
- ohazi 5y ago
  > driven by DARPA to get Raytheon imaging chips working with Intel AI chips Well that's a terrifying thought...
  - ohgodplsno 5y ago
    AI recognition of brown people can't be any worse than what the US currently does when bombing them, at least!
mmmBacon 5y ago
Marvell which might not have the resources to design a competitive interconnect solution themselves. I guess it depends on what you mean by interconnect. If you’re talking about >100GbE then the Marvell has a large market share in interconnect market for high speed Ethernet.
- stonogo 5y ago
  Marvell has nothing dense enough to meet these requirements. We're looking at 100GT/s, sure, but across millimeters, with physical connections measured in micrometers. It's a completely different technology to what Marvell makes.
  - mmmBacon 5y ago
    128GT/s in PCIE G4 is only 125Gb/s. Marvell has serial interfaces that do this today for Ethernet. Since PCIE is a multilane technology these lanes are quite low speed by comparison. Many folks who have these interfaces don’t have the expertise to produce the interface and actually purchase the IP from a 3rd party. Regarding pitch I’m not sure what your comment is based on but it’s doubtful you’re correct since pitch tends to be limited by the XTALK considerations not by fabrication. Since we are all using the same fabs we can all achieve the same minimum pitch supported by the ecosystem. Having said that even the pitch at these speeds is measured in microns and has been for a long time. I think what you probably mean is that Marvell’s devices use a lot of DSP and FEC for use in Ethernet. This is because those interfaces are much higher speed and include impairment compensation for both electrical and optical channels. The DSP and FEC add latency which in compute applications would be problematic.
phlipski 5y ago
There are companies today building various types of "multi-chip-modules" (MCM) and "systems-in-package" (SiP) that mix chips and passives from different vendors. - Octavo Systems puts Ti SOC's and PMIC's in a package with outside vendor DRAM and ROM chips. - NXP builds some auto parts with a mix of NXP chips on different process nodes and third party flash. I spent a few years designing these types of systems. In my mind the the biggest value of a standard like this is to push companies to make it worth their while to sell "known-good-die" (KGD) or fully-tested die. Modern chip manufacturing basically has a two part test flow - a partial test of each die on the wafer then after slicing and packaging each part goes through final test. Packaging is expensive and so imagine building a multi chip module which might have an SOC, DRAM, PMIC and FLASH bare dies and then it goes through final test and each of those dies had a 90% final test yield then the MCM might only have a 65% yield. That's a lot of money down the drain..... If I built the same part using fully tested die then my yields should be closer to 95-99% - basically the failures are not due to bad silicon, but bad packaging.... Right now it's tough to get companies to spend the resources on a KGD test program because the market is just too small/scattered. A standard helps to build a market. With that said - I haven't seen this standard yet. I just requested a copy. From the little info available on the website (https://www.uciexpress.org/ https://www.uciexpress.org/) it sounds like it's just an IO interconnect standard - along the lines of something like MIPI DSI + D-PHY. That's a good start but the dream of "lego" like chips will require standardized foot prints and pinouts which may just never be feasible but there are people exploring this idea....
- twic 5y ago
  Will chiplet vendors be selling actual physical chiplets, or still selling IP, but IP that has been fully validated through to manufacturing? If it's physical chiplets, are there any integration problems that come from trying to combine chiplets from different fabs in a single package? Variations in chemistry? How do you safely and cleanly transport unencapsulated chiplets?
  - phlipski 5y ago
    For the simplicity of this discussion let's just focus on companies selling physical chiplets. Assuming the company follows normal manufacturing processes (and assuming that company is "fabless" then this is a pretty safe assumption) then there is no risk of mixing different silicon from different vendors/fabs in a single package. This is being done today. Currently designers do have to take into account mixing parts that were designed for various package technologies. If a chip was designed for "flip-chp" and another chip for "wire-bond" then putting them both in the same package might require some different packaging techniques... That said - I'd assume if a company was going to build a chip and specifically market it for this new UCIe standard then they'd probably target a WLCSP type final process which is fairly common today. https://amkor.com/packaging/wafer-level-packaging/wlcsp/ https://amkor.com/packaging/wafer-level-packaging/wlcsp/

halJordan 5y ago

Your premise that it it is unlikely that there will be multi-vendor chiplets on a single chip is undermined by the industry coming together and creating a standard to use each other’s chiplets in a single chip.

kijiki 5y ago

https://ark.intel.com/content/www/us/en/ark/products/130409/intel-core-i78809g-processor-with-radeon-rx-vega-m-gh-graphics-8m-cache-up-to-4-20-ghz.html https://ark.intel.com/content/www/us/en/ark/products/130409/... Intel has already shipped a MCM with an Intel CPU and a AMD GPU, back in 2018. That probably just used PCIe, since cache coherence wasn't needed.

paulgerhardt 5y ago

The move to standardize the interposer was driven by DARPA to get Raytheon imaging chips working with Intel AI chips. See slide 109: https://www.darpa.mil/attachments/ERI-DAProposersDay_ConsolidatedSlides.pdf https://www.darpa.mil/attachments/ERI-DAProposersDay_Consoli...

ohazi 5y ago
> driven by DARPA to get Raytheon imaging chips working with Intel AI chips Well that's a terrifying thought...
- ohgodplsno 5y ago
  AI recognition of brown people can't be any worse than what the US currently does when bombing them, at least!

mmmBacon 5y ago

Marvell which might not have the resources to design a competitive interconnect solution themselves. I guess it depends on what you mean by interconnect. If you’re talking about >100GbE then the Marvell has a large market share in interconnect market for high speed Ethernet.

stonogo 5y ago
Marvell has nothing dense enough to meet these requirements. We're looking at 100GT/s, sure, but across millimeters, with physical connections measured in micrometers. It's a completely different technology to what Marvell makes.
- mmmBacon 5y ago
  128GT/s in PCIE G4 is only 125Gb/s. Marvell has serial interfaces that do this today for Ethernet. Since PCIE is a multilane technology these lanes are quite low speed by comparison. Many folks who have these interfaces don’t have the expertise to produce the interface and actually purchase the IP from a 3rd party. Regarding pitch I’m not sure what your comment is based on but it’s doubtful you’re correct since pitch tends to be limited by the XTALK considerations not by fabrication. Since we are all using the same fabs we can all achieve the same minimum pitch supported by the ecosystem. Having said that even the pitch at these speeds is measured in microns and has been for a long time. I think what you probably mean is that Marvell’s devices use a lot of DSP and FEC for use in Ethernet. This is because those interfaces are much higher speed and include impairment compensation for both electrical and optical channels. The DSP and FEC add latency which in compute applications would be problematic.

phlipski 5y ago

There are companies today building various types of "multi-chip-modules" (MCM) and "systems-in-package" (SiP) that mix chips and passives from different vendors. - Octavo Systems puts Ti SOC's and PMIC's in a package with outside vendor DRAM and ROM chips. - NXP builds some auto parts with a mix of NXP chips on different process nodes and third party flash. I spent a few years designing these types of systems. In my mind the the biggest value of a standard like this is to push companies to make it worth their while to sell "known-good-die" (KGD) or fully-tested die. Modern chip manufacturing basically has a two part test flow - a partial test of each die on the wafer then after slicing and packaging each part goes through final test. Packaging is expensive and so imagine building a multi chip module which might have an SOC, DRAM, PMIC and FLASH bare dies and then it goes through final test and each of those dies had a 90% final test yield then the MCM might only have a 65% yield. That's a lot of money down the drain..... If I built the same part using fully tested die then my yields should be closer to 95-99% - basically the failures are not due to bad silicon, but bad packaging.... Right now it's tough to get companies to spend the resources on a KGD test program because the market is just too small/scattered. A standard helps to build a market. With that said - I haven't seen this standard yet. I just requested a copy. From the little info available on the website (https://www.uciexpress.org/ https://www.uciexpress.org/) it sounds like it's just an IO interconnect standard - along the lines of something like MIPI DSI + D-PHY. That's a good start but the dream of "lego" like chips will require standardized foot prints and pinouts which may just never be feasible but there are people exploring this idea....

twic 5y ago
Will chiplet vendors be selling actual physical chiplets, or still selling IP, but IP that has been fully validated through to manufacturing? If it's physical chiplets, are there any integration problems that come from trying to combine chiplets from different fabs in a single package? Variations in chemistry? How do you safely and cleanly transport unencapsulated chiplets?
- phlipski 5y ago
  For the simplicity of this discussion let's just focus on companies selling physical chiplets. Assuming the company follows normal manufacturing processes (and assuming that company is "fabless" then this is a pretty safe assumption) then there is no risk of mixing different silicon from different vendors/fabs in a single package. This is being done today. Currently designers do have to take into account mixing parts that were designed for various package technologies. If a chip was designed for "flip-chp" and another chip for "wire-bond" then putting them both in the same package might require some different packaging techniques... That said - I'd assume if a company was going to build a chip and specifically market it for this new UCIe standard then they'd probably target a WLCSP type final process which is fairly common today. https://amkor.com/packaging/wafer-level-packaging/wlcsp/ https://amkor.com/packaging/wafer-level-packaging/wlcsp/