Every level of cache strikes a balance between latency & capacity. Bigger caches have higher latency; it's a fundamental property of caches. What you can concl

Every level of cache strikes a balance between latency & capacity. Bigger caches have higher latency; it's a fundamental property of caches. What you can conclude is that 0.5MB-2MB and 12-15 cycles of latency has been a steady sweet spot for L2 size for twenty years. Sidebar: it was a property of caches. 3D assembly may upend the local optima.