RISC-V does not have unused/unusable exceptions and tries not to expose internal details of implementation as much as possible. To show difference, OpenRISC ha

RISC-V does not have unused/unusable exceptions and tries not to expose internal details of implementation as much as possible. To show difference, OpenRISC has division-by-zero exception which is unnecessary - it can be ruled out by compiler or, if compiler did not rule it out, can be checked and triggered by comparison, conditional jump and special trap command. MIPS did exactly that almost fourty years ago. OpenRISC also has (optional) branch delay slot, which complicates out-of-order implementations and even in-order implementations with memory mapping unit - what state should you keep to properly handle MMU exception in the branch delay slot command? Alpha AXP, being the ISA that was designed to be useful for 20-25 years, ditched both of these in early 1990-th. RISC-V, which extends experience of RISC-IV (SPUR [1]) and other RISC designs, including POWER and SPARC, also does not sport these atrocities. [1] https://news.ycombinator.com/item?id=19266152 https://news.ycombinator.com/item?id=19266152 All in all, RISC-V represents an ISA that can be implemented differently with less effort than OpenRISC and, to be frank, most other RISC ISAs.