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> will "succeed" because there's no way for it to fail. It's like Linux. Didn't OpenRISC fail? https://en.wikipedia.org/wiki/OpenRISC https://en.wikipedia.org/

by als0 5y ago

> will "succeed" because there's no way for it to fail. It's like Linux. Didn't OpenRISC fail? https://en.wikipedia.org/wiki/OpenRISC https://en.wikipedia.org/wiki/OpenRISC Also there are different definitions of "succeed" from different viewpoints. In academia RISC-V is already a big success.

goodpoint 5y ago
Good point. How is RISC-V better than OpenRISC's ISA?
- tyingq 5y ago
  Mainline Linux kernel support is a fairly big plus.
- thesz 5y ago
  RISC-V does not have unused/unusable exceptions and tries not to expose internal details of implementation as much as possible. To show difference, OpenRISC has division-by-zero exception which is unnecessary - it can be ruled out by compiler or, if compiler did not rule it out, can be checked and triggered by comparison, conditional jump and special trap command. MIPS did exactly that almost fourty years ago. OpenRISC also has (optional) branch delay slot, which complicates out-of-order implementations and even in-order implementations with memory mapping unit - what state should you keep to properly handle MMU exception in the branch delay slot command? Alpha AXP, being the ISA that was designed to be useful for 20-25 years, ditched both of these in early 1990-th. RISC-V, which extends experience of RISC-IV (SPUR [1]) and other RISC designs, including POWER and SPARC, also does not sport these atrocities. [1] https://news.ycombinator.com/item?id=19266152 https://news.ycombinator.com/item?id=19266152 All in all, RISC-V represents an ISA that can be implemented differently with less effort than OpenRISC and, to be frank, most other RISC ISAs.
- panick21_ 5y ago
  They did not build on OpenRISC because it was originally mostly just a chip and it was 32 bit only. RISC-V started out with the goal of being capable of very small to really large chips and do 32 and 64 bit. OpenRISC did add 64 bit later but by that point RISC-V was already going.

by als0 5y ago

goodpoint 5y ago

Good point. How is RISC-V better than OpenRISC's ISA?

tyingq 5y ago
Mainline Linux kernel support is a fairly big plus.
thesz 5y ago
RISC-V does not have unused/unusable exceptions and tries not to expose internal details of implementation as much as possible. To show difference, OpenRISC has division-by-zero exception which is unnecessary - it can be ruled out by compiler or, if compiler did not rule it out, can be checked and triggered by comparison, conditional jump and special trap command. MIPS did exactly that almost fourty years ago. OpenRISC also has (optional) branch delay slot, which complicates out-of-order implementations and even in-order implementations with memory mapping unit - what state should you keep to properly handle MMU exception in the branch delay slot command? Alpha AXP, being the ISA that was designed to be useful for 20-25 years, ditched both of these in early 1990-th. RISC-V, which extends experience of RISC-IV (SPUR [1]) and other RISC designs, including POWER and SPARC, also does not sport these atrocities. [1] https://news.ycombinator.com/item?id=19266152 https://news.ycombinator.com/item?id=19266152 All in all, RISC-V represents an ISA that can be implemented differently with less effort than OpenRISC and, to be frank, most other RISC ISAs.
panick21_ 5y ago
They did not build on OpenRISC because it was originally mostly just a chip and it was 32 bit only. RISC-V started out with the goal of being capable of very small to really large chips and do 32 and 64 bit. OpenRISC did add 64 bit later but by that point RISC-V was already going.