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Jim Keller is overseeing a very large RISC-V core that should be around the same performance level as X1 or Zen 3. I guess we'll see what the ISA can do pretty

by hajile 5y ago

Jim Keller is overseeing a very large RISC-V core that should be around the same performance level as X1 or Zen 3. I guess we'll see what the ISA can do pretty soon. He said they were talking about open-sourcing the CPU block. If they did (the CPU isn't their core business), we could see lots of RISC-V competition popping up. The age of CPUs being commodity items seems to be approaching. https://youtu.be/KOHQQyAKY14?t=494 https://youtu.be/KOHQQyAKY14?t=494

mhh__ 5y ago
That is definitely a phat core but I wouldn't expect it to be exactly trading blows with Zen3 or alder lake given (that depends on one's definition of "around the same" I suppose) since the backend seems quite narrow. That might be all they need for AI however, going to watch the video tomorrow. It has big caches by the looks of things but the throughput is more like Zen2 depending on what they can clock it at. Either way I don't think anyone is seriously arguing you can't make a high-performance RISC-V process, but the thing is that scaling from (say) fast at memory and basic integer operations all the way up to all the sometimes wacky shit people want from their desktop machines will probably not be easy. It took Apple decades to do it with an ISA they helped design themselves.
- hajile 5y ago
  https://images.anandtech.com/doci/15813/A78-X1-crop-23.png https://images.anandtech.com/doci/15813/A78-X1-crop-23.png They didn’t mention how many branch units they have, but the ALU count is identical to X1. They have half the SIMD units, but each unit is twice the width which increases instruction density on high performance workloads.
ksec 5y ago
They are planning to open the Small CPU core, the packet processor and the vector processing unit. NOT the actual high performance RISC-V core. I also think the high performance here is a relative term to their small core.

by hajile 5y ago

mhh__ 5y ago

That is definitely a phat core but I wouldn't expect it to be exactly trading blows with Zen3 or alder lake given (that depends on one's definition of "around the same" I suppose) since the backend seems quite narrow. That might be all they need for AI however, going to watch the video tomorrow. It has big caches by the looks of things but the throughput is more like Zen2 depending on what they can clock it at. Either way I don't think anyone is seriously arguing you can't make a high-performance RISC-V process, but the thing is that scaling from (say) fast at memory and basic integer operations all the way up to all the sometimes wacky shit people want from their desktop machines will probably not be easy. It took Apple decades to do it with an ISA they helped design themselves.

hajile 5y ago
https://images.anandtech.com/doci/15813/A78-X1-crop-23.png https://images.anandtech.com/doci/15813/A78-X1-crop-23.png They didn’t mention how many branch units they have, but the ALU count is identical to X1. They have half the SIMD units, but each unit is twice the width which increases instruction density on high performance workloads.

ksec 5y ago

They are planning to open the Small CPU core, the packet processor and the vector processing unit. NOT the actual high performance RISC-V core. I also think the high performance here is a relative term to their small core.