The big problem of software filled TLBs is that taking an interrupt serializes the pipeline and is an inherently single-threaded operation. Interrupts themselve

The big problem of software filled TLBs is that taking an interrupt serializes the pipeline and is an inherently single-threaded operation. Interrupts themselves are very heavy weight on high performance cores too. You could handwave that way somewhat, but not the serial nature of it. Software filled just doesn't cut it for high performance cores. If an ISA defined a very small contained set of operations for TLB miss to program page table walking / TLB refill state machines that allowed the OS to define that behavior without taking an architectural interrupt that would be very cool. I suspect the hardware cost and complexity is not considered worthwhile though.