Virtual linear page table. Neat trick. I think ia64 had an option to do that as well. But I've never seen a really good study of them on a decent range of inter

Virtual linear page table. Neat trick. I think ia64 had an option to do that as well. But I've never seen a really good study of them on a decent range of interesting workloads. Primary TLB misses have no dependent memory accesses (just the PTE) but at a cost of another TLB entry. Could be a win in some cases. Nobody really does it anymore though, it could be there is not much appetite for the risk of trying out different virtual memory schemes these days.