You could also expand a TLB miss "ld r1, (r2)" inline to: movcsr r, pte_addr, r ldd r, (r) movcsr r, tlb_data, r ld r1, (r2) With appropri

You could also expand a TLB miss "ld r1, (r2)" inline to: movcsr r, pte_addr, r ldd r, (r) movcsr r, tlb_data, r ld r1, (r2) With appropriate traps as described above (that's essentially how I handle vectored CLIC interrupts on my RISCV)