4 ms·
That shouldn't be a problem to implement on an FPGA with a tiny bit of extra logic.
by russdill 5y ago
That shouldn't be a problem to implement on an FPGA with a tiny bit of extra logic.
- monocasa 5y agoTotally agreed, but you can't just throw the netlist at a fpga and expect the synthesizer to be happy is all I'm saying.