3 ms·
On RISC-V, I've seen the trick of swapping a register with the m/sscratch CSR in order to obtain one freely useable one. But this, of course, still is more over
by johndoe0815 5y ago
On RISC-V, I've seen the trick of swapping a register with the m/sscratch CSR in order to obtain one freely useable one. But this, of course, still is more overhead than on MIPS.
- Taniwha 5y agoyup, and a swap is more difficult because (depending on the design) is more likely to generate pipe bubbles. The mips also has (quite simple) magic hardware to convert the TLB miss address into a PTE address so that you can create the address you need in 1 clock, you could do some magic like that where the csr swap saved the reg in scratch and returned the PTE address, then the "write tlb entry" would also swap from scratch - you could do something like (pseudo code) : tlb_fault: movcsr r, pte_addr, r ldd r, (r) movcsr r, tlb_data, r mret (tlb entry would use the saved fault virtual address and the result from the ldd - the "ldd" would fault to a special pde vector if there's no TLB entry, the "movcsr r, tlb_data, r" would fault if you try and write an invalid PTE. BTW I think this only makes sense for simple RISC system - a massive super-scalar OOO system (like mine) would suffer massively if you had to toss all the (100+) instructions in the pipeline when you took a TLB miss
- Taniwha 5y ago(in other words it's a bit of an architectural dead end, like explicit branch delay slots if you want to grow a design past the simple risc stage)
- Taniwha 5y agoYou could also expand a TLB miss "ld r1, (r2)" inline to: movcsr r, pte_addr, r ldd r, (r) movcsr r, tlb_data, r ld r1, (r2) With appropriate traps as described above (that's essentially how I handle vectored CLIC interrupts on my RISCV)