3 ms·
BTW one of the coolest things is the way that MIPs (and other) systems do 2 level page tables - essentially they map the page tables into their virtual address
by Taniwha 5y ago
BTW one of the coolest things is the way that MIPs (and other) systems do 2 level page tables - essentially they map the page tables into their virtual address space (mapped by TLBs just like anything else) and then when they get a miss on a TLB fetch from a PTE they take a recursive trap and fill the TLB entry that matches the upper level PDE
A long time ago I worked on an x86 clone built on top of a 64-bit RISC core (pre amd64) we used this trick (and more) to do segmentation as well (to get around the then somewhat bogus Intel paging patents)
- throwawaylinux 5y agoVirtual linear page table. Neat trick. I think ia64 had an option to do that as well. But I've never seen a really good study of them on a decent range of interesting workloads. Primary TLB misses have no dependent memory accesses (just the PTE) but at a cost of another TLB entry. Could be a win in some cases. Nobody really does it anymore though, it could be there is not much appetite for the risk of trying out different virtual memory schemes these days.