3 ms·
> To get that full cache usage, you are still going to be using 32-bit integers wherever possible, but that means 3/4 of your pipeline goes to waste for most ca
by fennecfoxen 5y ago
> To get that full cache usage, you are still going to be using 32-bit integers wherever possible, but that means 3/4 of your pipeline goes to waste for most calculations.
I thought we were in an era of Dark Silicon where we are power/thermal constrained and it’s great to have lots of different special purpose parts of the die as long as you can turn them off when you’re not using them.
- hajile 5y agoNot even close. TSMC 10nm wafer $6,000 TSMC N7 wafer $9,000 TSMC N5 wafer $17,000 TSMC N3 wafer $20,000+ (exact pricing not public) Cutting core size and saving just a few mm^2 per chip means a few more chips per wafer which is critical to the bottom line given the radical price increases for each node. The only company this doesn't seem to be particularly true for is Apple. Apple has 2 large, high-performance cores, 4 relatively large efficiency cores (around A78 performance levels), a large GPU, and a whopping 32MB of SLC (system level cache). Meanwhile, Qualcomm's just released Snapdragon has ONE high-performance core (that is still smaller than Apple's performance cores) and 3 "medium" cores that are only a bit better than Apple's efficiency cores with a smaller GPU and a tiny 6MB SLC. Qualcomm has been so desperate to lower wafer/chip costs that they even moved to a terrible Samsung process. The only specialized units are HIGHLY specialized. They are fixed function (or near fixed function) video decoders or ML units and none of these actually add very much die area. GPUs have actually moved heavily toward general purpose computing (GP-GPU) specifically so they could reuse the die area for other non-graphics things.