3 ms·

We already have 128-bit processors, of sorts. They are called "vector units". ;) 128-bit integers could be useful for bignums. You can do bignum addition on ex

We already have 128-bit processors, of sorts. They are called "vector units". ;) 128-bit integers could be useful for bignums. You can do bignum addition on existing SIMD units but you'd have to use tricks to carry the carry between elements and to the next vector — and that makes the resulting code slower than using GPRs.[1] But I think this would still fit better in vector units than making the integer registers larger: The hw trend (ARM SVE, RISC-V V) is to make vector-width implementation-defined, starting at 128 bits in the low-end. 128-bit floating point is apparently a thing in scientific computing (but I've not seen it myself). 128-bit "pointers" exist in CHERI [2], where they are tagged capabilities that also store the bounds and access rights (rwx) for accessing memory through the pointer. Addresses are still 64-bit though. GPRs are still 64-bit. The caps are stored in a new register file. If you want to scale up address spaces, I think the biggest issue is not the number of bits but rather how to coordinate the address space to avoid collisions. One approach would be to re-introduce segmentation (pointer ⇒ segment ID and offset within segment), but unlike earlier system make each segment have its own local namespace of segment IDs it knows and translate between those when transferring pointers between segments. This idea is used by e.g. the research OS "Twizzer" [3], which was made for a large address space using NVRAM as RAM. I think this "pointer swizzling" could also be helped by hardware support. [1] Integer Addition and Carryout, by Alexander Yee <http://numberworld.org/y-cruncher/internals/addition.html http://numberworld.org/y-cruncher/internals/addition.html> [2] Capability Hardware Enhanced RISC Instructions (CHERI)<https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/ https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/> [3] Twizzler: An Operating System for Next-Generation Memory Hierarchies <https://www.ssrc.ucsc.edu/pub/bittman-ssrctr-17-01.html https://www.ssrc.ucsc.edu/pub/bittman-ssrctr-17-01.html>

jamal-kumar 5y ago
Very interesting. Does this have any implications for more accurate precision when floating points are being worked with in big numbers by any chance?
hajile 5y ago
128-bit vectors can do some stuff with integers, but most don't work at all for 128-bit floats which are where 128-bit is most important in hardware (because the software fallback is SLOW). I believe IBM POWER chips have both IEEE 128 floats (I think they call them a long double) and IEEE 128-bit decimal too. Outside of some very precise simulations though, I doubt there is very much demand.

jamal-kumar 5y ago

Very interesting. Does this have any implications for more accurate precision when floating points are being worked with in big numbers by any chance?

hajile 5y ago

128-bit vectors can do some stuff with integers, but most don't work at all for 128-bit floats which are where 128-bit is most important in hardware (because the software fallback is SLOW). I believe IBM POWER chips have both IEEE 128 floats (I think they call them a long double) and IEEE 128-bit decimal too. Outside of some very precise simulations though, I doubt there is very much demand.