5 ms·
I get the feeling the image from the link might just be wrong, though. It has 3 identical blocks in the user logic area. That doesn't fit the 8x8 FPGA story. Th
by marcan_42 5y ago
I get the feeling the image from the link might just be wrong, though. It has 3 identical blocks in the user logic area. That doesn't fit the 8x8 FPGA story. There's no factor of 3 there. Maybe they just used a random example built on the same platform?
Edit: yup, they just picked a pretty picture they had of what was apparently the first design in MPW1. You can browse it here:
https://siliconpr0n.org/map/gsky/mpw1-00010001/mz_mit10x/ https://siliconpr0n.org/map/gsky/mpw1-00010001/mz_mit10x/
Almost certainly not the actual FPGA design.
- kop316 5y agoI mean...in my mind, that raises more questions. All of the "Additional Cool stuff" to be implies that it was fabbed out on mpw-1 and they have tested it. Why take a random image then if you have die shots or a picture of the GDS? Then again, the low power consumption picture looks to be measuring the SPI flash? that is far too little pins for the FPGA.