4 ms·

8x8, so 64 4-luts and 64 flipflops? I'm not sure what I could build with that. Maybe a frequency counter with a SPI output, not much more.

marcan_42 5y ago
Yeah, that's a bit ridiculous. The smallest commercial FPGA you can buy, as far as I know, is the smallest MachXO2 with 256 LUTs, and that's already in the "a little bit of glue logic" territory. How do they do anything useful with 64 LUTs? With 38 I/Os, you're going to spend all your LUTs just interfacing with them... Am I missing something here? Edit: if this is the right project, then I see most of the I/Os aren't actually user I/Os in this design. https://github.com/Manarabdelaty/Caravel-OpenFPGA-EF https://github.com/Manarabdelaty/Caravel-OpenFPGA-EF
cpldcpu 5y ago
This CPU should fit :) https://github.com/cpldcpu/MCPU https://github.com/cpldcpu/MCPU
- aappleby 5y ago
  CPLDs handle programmable logic much differently than FPGAs - it might not actually fit.
  - deleted 5y ago
    [deleted]
  - cpldcpu 5y ago
    nah, it will easily fit. not sure about routing ressources though. === CPU8BIT2 === Number of wires: 319 Number of wire bits: 3029 Number of public wires: 38 Number of public wire bits: 209 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 79 $_DFF_PP0_ 24 $lut 55
eternityforest 5y ago
I don't think I could build much of anything interesting at all. Maybe a modulator for some obscure LED protocol that would probably be just fine in software on a 50 cent MCU anyway. But it is something that's never been done before, or at least has rarely been done this cheap.
ur-whale 5y ago
> I'm not sure what I could build with that A hardware true random number generator using ring oscillators
- denton-scratch 5y ago
  For which you'd want at least two rings, with mutually-prime numbers of inverters - e.g. 53 and 11. But you'll also need a serial-in parallel-out shift register, which I guess you can probably do with a dozen gates. So maybe you could have rings of 41 and 11. Would it work? How could you avoid entrainment between the two rings? I tried this using a handful of TTL chips and a breadboard, but I'm not good at this kind of thing, and it didn't work (or rather, I couldn't prove it was working).
  - ur-whale 5y ago
    >For which you'd want at least two rings, with mutually-prime numbers of inverters Why? I was under the impression that all that mattered was the phase noise in the ring oscillators (and therefore the phase drift)? Also, not sure why would you need a shift register? Just something that samples the output of the TRNG on a pin at a reasonably low freq and bitbangs what it gets on an output pin hooked up to the RX pin a serial-USB thingie should do the trick.
    - denton-scratch 5y ago
      Well, I understand the principle to be that you use one ring oscillator to sample the state of the other; then you sample the output of the first oscillator on a clock. Phase noise just makes both oscillators more-or-less chaotic. How are you supposed to measure the phase noise? Yes, you could use a serial-USB chip, and collect one bit at a time. So you're right, there's no need for a shift register. Mutually prime: isn't it desirable that the sampling oscillator runs substantially slower than the sampled oscillator? You don't want successive samples to be from the same cycle of the sampled oscillator. I'm handwaving about mutual primality; but I'm thinking that you want to maximise the length of cycle over which the two oscillators would be expected to coincide, absent phase noise. I suppose having more inverters in each ring would increase the influence of phase noise, and increase the combined cycle length. And I still don't know how you avoid the two oscillators becoming entrained - they can influence one-another through the supply line.
krasin 5y ago
Yes, it's very limited. Personally, I backed for two reasons: 1. It will add a nice open-source reference design for a (small) FPGA that is compatible with the open-source SkyWater PDK. I am sure someone will take it and improve upon. 2. I am curious to try building a small batch of my own chips on this process (for a hobby project), but while I am somewhat comfortable with designing digital logic, I am less confident in my ability to take a chip and be able to communicate with it. By paying ~$80, I will be getting half of the experience (which would cost ~$10k otherwise)
- throwaway81523 5y ago
  It's pretty bogus for them to even call such a thing an fpga. Why did they design it that way?
  - krasin 5y ago
    For the first point, I think they are fine: FPGA stands for field-programmable gate array. This is exactly what they make, even though the array is very small. As for the question, I don't know. But they have a comment section, maybe it's worth asking them directly?

marcan_42 5y ago

Yeah, that's a bit ridiculous. The smallest commercial FPGA you can buy, as far as I know, is the smallest MachXO2 with 256 LUTs, and that's already in the "a little bit of glue logic" territory. How do they do anything useful with 64 LUTs? With 38 I/Os, you're going to spend all your LUTs just interfacing with them... Am I missing something here? Edit: if this is the right project, then I see most of the I/Os aren't actually user I/Os in this design. https://github.com/Manarabdelaty/Caravel-OpenFPGA-EF https://github.com/Manarabdelaty/Caravel-OpenFPGA-EF

cpldcpu 5y ago

This CPU should fit :) https://github.com/cpldcpu/MCPU https://github.com/cpldcpu/MCPU

aappleby 5y ago
CPLDs handle programmable logic much differently than FPGAs - it might not actually fit.
- deleted 5y ago
  [deleted]
- cpldcpu 5y ago
  nah, it will easily fit. not sure about routing ressources though. === CPU8BIT2 === Number of wires: 319 Number of wire bits: 3029 Number of public wires: 38 Number of public wire bits: 209 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 79 $_DFF_PP0_ 24 $lut 55

eternityforest 5y ago

I don't think I could build much of anything interesting at all. Maybe a modulator for some obscure LED protocol that would probably be just fine in software on a 50 cent MCU anyway. But it is something that's never been done before, or at least has rarely been done this cheap.

ur-whale 5y ago

> I'm not sure what I could build with that A hardware true random number generator using ring oscillators

denton-scratch 5y ago
For which you'd want at least two rings, with mutually-prime numbers of inverters - e.g. 53 and 11. But you'll also need a serial-in parallel-out shift register, which I guess you can probably do with a dozen gates. So maybe you could have rings of 41 and 11. Would it work? How could you avoid entrainment between the two rings? I tried this using a handful of TTL chips and a breadboard, but I'm not good at this kind of thing, and it didn't work (or rather, I couldn't prove it was working).
- ur-whale 5y ago
  >For which you'd want at least two rings, with mutually-prime numbers of inverters Why? I was under the impression that all that mattered was the phase noise in the ring oscillators (and therefore the phase drift)? Also, not sure why would you need a shift register? Just something that samples the output of the TRNG on a pin at a reasonably low freq and bitbangs what it gets on an output pin hooked up to the RX pin a serial-USB thingie should do the trick.
  - denton-scratch 5y ago
    Well, I understand the principle to be that you use one ring oscillator to sample the state of the other; then you sample the output of the first oscillator on a clock. Phase noise just makes both oscillators more-or-less chaotic. How are you supposed to measure the phase noise? Yes, you could use a serial-USB chip, and collect one bit at a time. So you're right, there's no need for a shift register. Mutually prime: isn't it desirable that the sampling oscillator runs substantially slower than the sampled oscillator? You don't want successive samples to be from the same cycle of the sampled oscillator. I'm handwaving about mutual primality; but I'm thinking that you want to maximise the length of cycle over which the two oscillators would be expected to coincide, absent phase noise. I suppose having more inverters in each ring would increase the influence of phase noise, and increase the combined cycle length. And I still don't know how you avoid the two oscillators becoming entrained - they can influence one-another through the supply line.

krasin 5y ago

Yes, it's very limited. Personally, I backed for two reasons: 1. It will add a nice open-source reference design for a (small) FPGA that is compatible with the open-source SkyWater PDK. I am sure someone will take it and improve upon. 2. I am curious to try building a small batch of my own chips on this process (for a hobby project), but while I am somewhat comfortable with designing digital logic, I am less confident in my ability to take a chip and be able to communicate with it. By paying ~$80, I will be getting half of the experience (which would cost ~$10k otherwise)

throwaway81523 5y ago
It's pretty bogus for them to even call such a thing an fpga. Why did they design it that way?
- krasin 5y ago
  For the first point, I think they are fine: FPGA stands for field-programmable gate array. This is exactly what they make, even though the array is very small. As for the question, I don't know. But they have a comment section, maybe it's worth asking them directly?