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The chip ignite path does not require designs to be published, unlike the Google sponsored MPWx tapeouts.
by commandpaul 5y ago
The chip ignite path does not require designs to be published, unlike the Google sponsored MPWx tapeouts.
- kop316 5y agoI get that, but the link literally says: "The Open Source FPGA ASIC". With that in the title, I would expect to be able to find the source of the FPGA.
- snvzz 5y agoRequired or not, it is desirable.
- krasin 5y agoMy guess would be that the first prototype that they made was too buggy to publish. The promise is that they will share the final design, and I am fine with that. (I am not affiliated with the project, but backed it)
- krasin 5y agoUpdate: marcan_42 apparently found it: https://efabless.com/projects/33 https://efabless.com/projects/33
- kop316 5y agoI don't think they are the same: Look at the picture in it versus in the link: https://groupgets-files.s3.amazonaws.com/Efabless/open-source-logo-on-caravel-min.jpg https://groupgets-files.s3.amazonaws.com/Efabless/open-sourc... They are different. Also, if you go to https://vlsicad.ucsd.edu/Publications/Conferences/383/c383.pdf https://vlsicad.ucsd.edu/Publications/Conferences/383/c383.p... Figure 6: You can find the image from the link (top left), and the on ehtat you linked (bottom left), so they are two different projects.
- kop316 5y agoAccording to this website: MPW-1 had a hold time violation in it's clock tree, so the RISC-V is unusable. https://www.zerotoasiccourse.com/post/mpw1-bringup/ https://www.zerotoasiccourse.com/post/mpw1-bringup/
- makomk 5y agoYikes. If I'm understanding that correctly every chip that came back from MPW-1 was more or less unusable - they were all required to gate access to I/Os behind the same management processor provided by the company organising the run, and because that management processor was broken they couldn't configure the I/Os to route through to their own designs.
- kop316 5y agoYeah that is my understanding too. You REALLY don't want a hold time violation, as you have to go in and edit the chip circuitry to fix that.
- commandpaul 5y agoLooks like this has been put together by Efabless themselves. I dont think the rtl would be too different from OpenFPGA(https://github.com/lnis-uofu/OpenFPGA https://github.com/lnis-uofu/OpenFPGA) married to the caravel f/w.