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Clear – Open-Source FPGA ASIC
- kristianpaul 5y agoThis looks more like a PLA wired to a CPU
- cpldcpu 5y agoI think it's a great initiative. However, marrying it to Caravel means that it basically a prototype and far away from a standalone product. Would be great to see a path to a real OSHW ASIC. That would require either a substantially larger crowd funding initiative or somehow setting up an ecosystem with fixed die and package options for OSHW IC products. I don't think the costs would be as high as everyone thinks, but the effort and time investment would be significant.
- mlatu 5y agoare they offering to turn your fpga design into an actual asic? i mean, am i missing something or did they slap "ASIC" on that product just for good measure in case someone isnt looking for "FPGA" (so for SEO reasons)?
- outsomnia 5y agoNo... they are making their own FPGA by fabbing their own ASIC. I agree it's confusing but it is what they called it. It's like an old Xilinx 2064 with a risc-V added on top, except the chip itself is OSSHW, not just the board.
- krasin 5y agoThis is actually something completely different. :) This is a show case for eFabless that uses SkyWater PDK to build actual ASICs on a 130nm process. They are making a toy 8x8 FPGA, just so that people can play with an FPGA ASIC that was custom manufactured for that group buy. See https://efabless.com/chipignite/ https://efabless.com/chipignite/
- jepler 5y agoLike others in the thread, I'm entranced by the idea. However, the lack of github links for the "open source" of this ASIC have put me right off of becoming a backer. It's a dang shame that we have to spend time & effort in this thread saying 'maybe _this_ is the source -- no, I think it's _that_'. In my view, actually showing your source (with all its warts and TODOs) is something you need to do from the moment you're out in public talking about how your product is Open Source, not hopefully sometime later. Basically, we've arrived at the moment where either your open source is on github, or it needs to be treated as not open source. Otherwise, especially if the fulfillment end goes pear shaped, it's way too easy to fall into a trap where the source simply never gets released despite all your initial intentions.
- voakbasda 5y agoI love to see GitHub used as a generic term for a hosted repository service. I would enjoy seeing that trademark continue its march to become a completely generic term. There are more options than GitHub for publishing source code. If anything, publishing on GitHub is an instant strike against openness, because Microsoft should not be trusted. Even GitLab would be a better place to publish, iff only as a mirror. So, yes, I agree. Lack of readily available source code on even the lowest common denominator hosting service should be a huge red flag when evaluating any project like this.
- kop316 5y agoAm I missing something or is the final source for the caravel user project missing? I cannot find it here: https://efabless.com/projects/shuttle_name/MPW-1 https://efabless.com/projects/shuttle_name/MPW-1 Nor here (since I think it is by efabless?) https://github.com/orgs/efabless/repositories https://github.com/orgs/efabless/repositories
- marcan_42 5y agoIsn't it this one? https://efabless.com/projects/33 https://efabless.com/projects/33
- kop316 5y agoI thought so too, but look at the picture in it versus in the link: https://groupgets-files.s3.amazonaws.com/Efabless/open-source-logo-on-caravel-min.jpg https://groupgets-files.s3.amazonaws.com/Efabless/open-sourc... They are different. Also, if you go to https://vlsicad.ucsd.edu/Publications/Conferences/383/c383.pdf https://vlsicad.ucsd.edu/Publications/Conferences/383/c383.p... Figure 6: You can find the image from the link (top left), and the on ehtat you linked (bottom left), so they are two different projects.
- marcan_42 5y agoI get the feeling the image from the link might just be wrong, though. It has 3 identical blocks in the user logic area. That doesn't fit the 8x8 FPGA story. There's no factor of 3 there. Maybe they just used a random example built on the same platform? Edit: yup, they just picked a pretty picture they had of what was apparently the first design in MPW1. You can browse it here: https://siliconpr0n.org/map/gsky/mpw1-00010001/mz_mit10x/ https://siliconpr0n.org/map/gsky/mpw1-00010001/mz_mit10x/ Almost certainly not the actual FPGA design.
- kop316 5y agoI mean...in my mind, that raises more questions. All of the "Additional Cool stuff" to be implies that it was fabbed out on mpw-1 and they have tested it. Why take a random image then if you have die shots or a picture of the GDS? Then again, the low power consumption picture looks to be measuring the SPI flash? that is far too little pins for the FPGA.
- aappleby 5y ago8x8, so 64 4-luts and 64 flipflops? I'm not sure what I could build with that. Maybe a frequency counter with a SPI output, not much more.
- marcan_42 5y agoYeah, that's a bit ridiculous. The smallest commercial FPGA you can buy, as far as I know, is the smallest MachXO2 with 256 LUTs, and that's already in the "a little bit of glue logic" territory. How do they do anything useful with 64 LUTs? With 38 I/Os, you're going to spend all your LUTs just interfacing with them... Am I missing something here? Edit: if this is the right project, then I see most of the I/Os aren't actually user I/Os in this design. https://github.com/Manarabdelaty/Caravel-OpenFPGA-EF https://github.com/Manarabdelaty/Caravel-OpenFPGA-EF
- cpldcpu 5y agoThis CPU should fit :) https://github.com/cpldcpu/MCPU https://github.com/cpldcpu/MCPU
- aappleby 5y agoCPLDs handle programmable logic much differently than FPGAs - it might not actually fit.
- deleted 5y ago[deleted]
- cpldcpu 5y agonah, it will easily fit. not sure about routing ressources though. === CPU8BIT2 === Number of wires: 319 Number of wire bits: 3029 Number of public wires: 38 Number of public wire bits: 209 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 79 $_DFF_PP0_ 24 $lut 55
- 5y ago