3 ms·
Such a waste, but the die voltage stacking is interesting. I wonder if GPGPU devices could use the same thing if the cores were sufficiently lockstep. > That a
by mkj 5y ago
Such a waste, but the die voltage stacking is interesting. I wonder if GPGPU devices could use the same thing if the cores were sufficiently lockstep.
> That allows an input voltage of 8.875 V to be divided into 355 mV across each ganged ASICs group
- RL_Quine 5y agoIt's not novel, it's been used since some of the very first mining ASICS. The reason you don't see it anywhere else is that the matching needs to be very good, down to giving chips busy work if they are idle otherwise you get interesting results. https://i.imgur.com/hAss6mY.jpeg https://i.imgur.com/hAss6mY.jpeg They are presumably ganging them at each voltage level to try to reduce the candescence.